1 """Computation Unit (aka "ALU Manager").
3 Manages a Pipeline or FSM, ensuring that the start and end time are 100%
4 monitored. At no time may the ALU proceed without this module notifying
5 the Dependency Matrices. At no time is a result production "abandoned".
6 This module blocks (indicates busy) starting from when it first receives
7 an opcode until it receives notification that
8 its result(s) have been successfully stored in the regfile(s)
10 Documented at http://libre-soc.org/3d_gpu/architecture/compunit
13 from soc
.experiment
.alu_fsm
import Shifter
, CompFSMOpSubset
14 from soc
.fu
.alu
.alu_input_record
import CompALUOpSubset
15 from soc
.experiment
.alu_hier
import ALU
, DummyALU
16 from soc
.experiment
.compalu_multi
import MultiCompUnit
17 from soc
.decoder
.power_enums
import MicrOp
18 from nmutil
.gtkw
import write_gtkw
19 from nmigen
import Module
, Signal
20 from nmigen
.cli
import rtlil
22 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
23 # Also, check out the cxxsim nmigen branch, and latest yosys from git
24 from nmutil
.sim_tmp_alternative
import (Simulator
, Settle
, is_engine_pysim
,
34 class OperandProducer
:
36 Produces an operand when requested by the Computation Unit
37 (`dut` parameter), using the `rel_o` / `go_i` handshake.
39 Attaches itself to the `dut` operand indexed by `op_index`.
41 Has a programmable delay between the assertion of `rel_o` and the
44 Data is presented only during the cycle in which `go_i` is active.
46 It adds itself as a passive process to the simulation (`sim` parameter).
47 Since it is passive, it will not hang the simulation, and does not need a
48 flag to terminate itself.
50 def __init__(self
, sim
, dut
, op_index
):
51 self
.count
= Signal(8, name
=f
"src{op_index + 1}_count")
52 """ transaction counter"""
53 # data and handshake signals from the DUT
54 self
.port
= dut
.src_i
[op_index
]
55 self
.go_i
= dut
.rd
.go_i
[op_index
]
56 self
.rel_o
= dut
.rd
.rel_o
[op_index
]
57 # transaction parameters, passed via signals
58 self
.delay
= Signal(8)
59 self
.data
= Signal
.like(self
.port
)
60 # add ourselves to the simulation process list
61 sim
.add_sync_process(self
._process
)
66 # Settle() is needed to give a quick response to
69 # wait for rel_o to become active
70 while not (yield self
.rel_o
):
73 # read the transaction parameters
74 delay
= (yield self
.delay
)
75 data
= (yield self
.data
)
76 # wait for `delay` cycles
77 for _
in range(delay
):
79 # activate go_i and present data, for one cycle
81 yield self
.port
.eq(data
)
82 yield self
.count
.eq(self
.count
+ 1)
87 def send(self
, data
, delay
):
89 Schedules the module to send some `data`, counting `delay` cycles after
90 `rel_i` becomes active.
92 To be called from the main test-bench process,
93 it returns in the same cycle.
95 Communication with the worker process is done by means of
96 combinatorial simulation-only signals.
99 yield self
.data
.eq(data
)
100 yield self
.delay
.eq(delay
)
103 class ResultConsumer
:
105 Consumes a result when requested by the Computation Unit
106 (`dut` parameter), using the `rel_o` / `go_i` handshake.
108 Attaches itself to the `dut` result indexed by `op_index`.
110 Has a programmable delay between the assertion of `rel_o` and the
113 Data is retrieved only during the cycle in which `go_i` is active.
115 It adds itself as a passive process to the simulation (`sim` parameter).
116 Since it is passive, it will not hang the simulation, and does not need a
117 flag to terminate itself.
119 def __init__(self
, sim
, dut
, op_index
):
120 self
.count
= Signal(8, name
=f
"dest{op_index + 1}_count")
121 """ transaction counter"""
122 # data and handshake signals from the DUT
123 self
.port
= dut
.dest
[op_index
]
124 self
.go_i
= dut
.wr
.go_i
[op_index
]
125 self
.rel_o
= dut
.wr
.rel_o
[op_index
]
126 # transaction parameters, passed via signals
127 self
.delay
= Signal(8)
128 self
.expected
= Signal
.like(self
.port
)
129 # add ourselves to the simulation process list
130 sim
.add_sync_process(self
._process
)
135 # Settle() is needed to give a quick response to
136 # the zero delay case
138 # wait for rel_o to become active
139 while not (yield self
.rel_o
):
142 # read the transaction parameters
143 delay
= (yield self
.delay
)
144 expected
= (yield self
.expected
)
145 # wait for `delay` cycles
146 for _
in range(delay
):
148 # activate go_i for one cycle
149 yield self
.go_i
.eq(1)
150 yield self
.count
.eq(self
.count
+ 1)
152 # check received data against the expected value
153 result
= (yield self
.port
)
154 assert result
== expected
,\
155 f
"expected {expected}, received {result}"
156 yield self
.go_i
.eq(0)
157 yield self
.port
.eq(0)
159 def receive(self
, expected
, delay
):
161 Schedules the module to receive some result,
162 counting `delay` cycles after `rel_i` becomes active.
163 As 'go_i' goes active, check the result with `expected`.
165 To be called from the main test-bench process,
166 it returns in the same cycle.
168 Communication with the worker process is done by means of
169 combinatorial simulation-only signals.
171 yield self
.expected
.eq(expected
)
172 yield self
.delay
.eq(delay
)
175 def op_sim(dut
, a
, b
, op
, inv_a
=0, imm
=0, imm_ok
=0, zero_a
=0):
176 yield dut
.issue_i
.eq(0)
178 yield dut
.src_i
[0].eq(a
)
179 yield dut
.src_i
[1].eq(b
)
180 yield dut
.oper_i
.insn_type
.eq(op
)
181 yield dut
.oper_i
.invert_in
.eq(inv_a
)
182 yield dut
.oper_i
.imm_data
.data
.eq(imm
)
183 yield dut
.oper_i
.imm_data
.ok
.eq(imm_ok
)
184 yield dut
.oper_i
.zero_a
.eq(zero_a
)
185 yield dut
.issue_i
.eq(1)
187 yield dut
.issue_i
.eq(0)
189 if not imm_ok
or not zero_a
:
190 yield dut
.rd
.go_i
.eq(0b11)
193 rd_rel_o
= yield dut
.rd
.rel_o
194 print("rd_rel", rd_rel_o
)
197 yield dut
.rd
.go_i
.eq(0)
201 if len(dut
.src_i
) == 3:
202 yield dut
.rd
.go_i
.eq(0b100)
205 rd_rel_o
= yield dut
.rd
.rel_o
206 print("rd_rel", rd_rel_o
)
209 yield dut
.rd
.go_i
.eq(0)
213 req_rel_o
= yield dut
.wr
.rel_o
214 result
= yield dut
.data_o
215 print("req_rel", req_rel_o
, result
)
217 req_rel_o
= yield dut
.wr
.rel_o
218 result
= yield dut
.data_o
219 print("req_rel", req_rel_o
, result
)
223 yield dut
.wr
.go_i
[0].eq(1)
225 result
= yield dut
.data_o
227 print("result", result
)
228 yield dut
.wr
.go_i
[0].eq(0)
233 def scoreboard_sim_fsm(dut
, producers
, consumers
):
235 # stores the operation count
238 def op_sim_fsm(a
, b
, direction
, expected
, delays
):
239 print("op_sim_fsm", a
, b
, direction
, expected
)
240 yield dut
.issue_i
.eq(0)
242 # forward data and delays to the producers and consumers
243 yield from producers
[0].send(a
, delays
[0])
244 yield from producers
[1].send(b
, delays
[1])
245 yield from consumers
[0].receive(expected
, delays
[2])
246 # submit operation, and assert issue_i for one cycle
247 yield dut
.oper_i
.sdir
.eq(direction
)
248 yield dut
.issue_i
.eq(1)
250 yield dut
.issue_i
.eq(0)
251 # wait for busy to be negated
253 while (yield dut
.busy_o
):
256 # update the operation count
258 op_count
= (op_count
+ 1) & 255
259 # check that producers and consumers have the same count
260 # this assures that no data was left unused or was lost
261 assert (yield producers
[0].count
) == op_count
262 assert (yield producers
[1].count
) == op_count
263 assert (yield consumers
[0].count
) == op_count
266 # operand 1 arrives immediately
267 # operand 2 arrives after operand 1
268 # write data is accepted immediately
269 yield from op_sim_fsm(13, 2, 1, 3, [0, 2, 0])
271 # operand 2 arrives immediately
272 # operand 1 arrives after operand 2
273 # write data is accepted after some delay
274 yield from op_sim_fsm(3, 4, 0, 48, [2, 0, 2])
276 # operands 1 and 2 arrive at the same time
277 # write data is accepted after some delay
278 yield from op_sim_fsm(21, 0, 0, 21, [1, 1, 1])
281 def scoreboard_sim_dummy(dut
):
282 result
= yield from op_sim(dut
, 5, 2, MicrOp
.OP_NOP
, inv_a
=0,
284 assert result
== 5, result
286 result
= yield from op_sim(dut
, 9, 2, MicrOp
.OP_NOP
, inv_a
=0,
288 assert result
== 9, result
292 """ALU Operation issuer
294 Issues operations to the DUT"""
295 def __init__(self
, dut
, sim
):
297 self
.zero_a_count
= 0
298 self
.imm_ok_count
= 0
300 # create one operand producer for each input port
301 self
.producers
= list()
302 for i
in range(len(dut
.src_i
)):
303 self
.producers
.append(OperandProducer(sim
, dut
, i
))
304 # create one result consumer for each output port
305 self
.consumers
= list()
306 for i
in range(len(dut
.dest
)):
307 self
.consumers
.append(ResultConsumer(sim
, dut
, i
))
308 def issue(self
, src_i
, op
, expected
, src_delays
, dest_delays
,
309 inv_a
=0, imm
=0, imm_ok
=0, zero_a
=0):
310 """Executes the issue operation"""
312 producers
= self
.producers
313 consumers
= self
.consumers
314 yield dut
.issue_i
.eq(0)
316 # forward data and delays to the producers and consumers
317 # first, send special cases (with zero_a and/or imm_ok)
319 yield from producers
[0].send(src_i
[0], src_delays
[0])
321 yield from producers
[1].send(src_i
[1], src_delays
[1])
322 # then, send the rest (if any)
323 for i
in range(2, len(producers
)):
324 yield from producers
[i
].send(src_i
[i
], src_delays
[i
])
325 for i
in range(len(consumers
)):
326 yield from consumers
[i
].receive(expected
, dest_delays
[i
])
327 # submit operation, and assert issue_i for one cycle
328 yield dut
.oper_i
.insn_type
.eq(op
)
329 yield dut
.oper_i
.invert_in
.eq(inv_a
)
330 yield dut
.oper_i
.imm_data
.data
.eq(imm
)
331 yield dut
.oper_i
.imm_data
.ok
.eq(imm_ok
)
332 yield dut
.oper_i
.zero_a
.eq(zero_a
)
333 yield dut
.issue_i
.eq(1)
335 yield dut
.issue_i
.eq(0)
336 # wait for busy to be negated
338 while (yield dut
.busy_o
):
341 # update the operation count
342 self
.op_count
= (self
.op_count
+ 1) & 255
343 # On zero_a and imm_ok executions, the producer counters will fall
344 # behind. But, by summing the following counts, the invariant is
347 self
.zero_a_count
= self
.zero_a_count
+ 1
349 self
.imm_ok_count
= self
.imm_ok_count
+ 1
350 # check that producers and consumers have the same count
351 # this assures that no data was left unused or was lost
352 # first, check special cases (zero_a and imm_ok)
353 assert (yield producers
[0].count
) + self
.zero_a_count
== self
.op_count
354 assert (yield producers
[1].count
) + self
.imm_ok_count
== self
.op_count
355 # then, check the rest (if any)
356 for i
in range(2, len(producers
)):
357 assert (yield producers
[i
].count
) == self
.op_count
358 for i
in range(len(consumers
)):
359 assert (yield consumers
[i
].count
) == self
.op_count
362 def scoreboard_sim(op
):
363 # zero (no) input operands test
365 yield from op
.issue([5, 2], MicrOp
.OP_ADD
,
366 zero_a
=1, imm
=8, imm_ok
=1,
368 src_delays
=[0, 2], dest_delays
=[0])
370 yield from op
.issue([5, 2], MicrOp
.OP_ADD
,
371 inv_a
=0, imm
=8, imm_ok
=1,
373 src_delays
=[2, 0], dest_delays
=[2])
375 yield from op
.issue([5, 2], MicrOp
.OP_ADD
,
377 src_delays
=[1, 1], dest_delays
=[1])
379 yield from op
.issue([5, 2], MicrOp
.OP_ADD
, inv_a
=1,
381 src_delays
=[1, 2], dest_delays
=[0])
383 yield from op
.issue([5, 2], MicrOp
.OP_ADD
, zero_a
=1,
385 src_delays
=[2, 0], dest_delays
=[1])
387 # test combinatorial zero-delay operation
388 # In the test ALU, any operation other than ADD, MUL or SHR
389 # is zero-delay, and do a subtraction.
390 yield from op
.issue([5, 2], MicrOp
.OP_NOP
,
392 src_delays
=[0, 1], dest_delays
=[2])
395 def test_compunit_fsm():
396 top
= "top.cu" if is_engine_pysim() else "cu"
398 'in': {'color': 'orange'},
399 'out': {'color': 'yellow'},
403 ('operation port', {'color': 'red'}, [
404 'cu_issue_i', 'cu_busy_o',
405 {'comment': 'operation'},
406 'oper_i_None__sdir']),
407 ('operand 1 port', 'in', [
408 ('cu_rd__rel_o[1:0]', {'bit': 1}),
409 ('cu_rd__go_i[1:0]', {'bit': 1}),
411 ('operand 2 port', 'in', [
412 ('cu_rd__rel_o[1:0]', {'bit': 0}),
413 ('cu_rd__go_i[1:0]', {'bit': 0}),
415 ('result port', 'out', [
416 'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[7:0]']),
417 ('alu', {'module': top
+'.alu'}, [
418 ('prev port', 'in', [
419 'op__sdir', 'p_data_i[7:0]', 'p_shift_i[7:0]',
420 'p_valid_i', 'p_ready_o']),
421 ('next port', 'out', [
422 'n_data_o[7:0]', 'n_valid_o', 'n_ready_i']),
424 ('debug', {'module': 'top'},
425 ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])
429 "test_compunit_fsm1.gtkw",
430 "test_compunit_fsm1.vcd",
436 dut
= MultiCompUnit(8, alu
, CompFSMOpSubset
)
437 m
.submodules
.cu
= dut
439 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
440 with
open("test_compunit_fsm1.il", "w") as f
:
446 # create one operand producer for each input port
447 prod_a
= OperandProducer(sim
, dut
, 0)
448 prod_b
= OperandProducer(sim
, dut
, 1)
449 # create an result consumer for the output port
450 cons
= ResultConsumer(sim
, dut
, 0)
451 sim
.add_sync_process(wrap(scoreboard_sim_fsm(dut
,
454 sim_writer
= sim
.write_vcd('test_compunit_fsm1.vcd',
455 traces
=[prod_a
.count
,
466 dut
= MultiCompUnit(16, alu
, CompALUOpSubset
)
467 m
.submodules
.cu
= dut
469 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
470 with
open("test_compunit1.il", "w") as f
:
476 # create an operation issuer
478 sim
.add_sync_process(wrap(scoreboard_sim(op
)))
479 sim_writer
= sim
.write_vcd('test_compunit1.vcd')
484 class CompUnitParallelTest
:
485 def __init__(self
, dut
):
488 # Operation cycle should not take longer than this:
489 self
.MAX_BUSY_WAIT
= 50
491 # Minimum duration in which issue_i will be kept inactive,
492 # during which busy_o must remain low.
493 self
.MIN_BUSY_LOW
= 5
495 # Number of cycles to stall until the assertion of go.
496 # One value, for each port. Can be zero, for no delay.
497 self
.RD_GO_DELAY
= [0, 3]
499 # store common data for the input operation of the processes
502 self
.inv_a
= self
.zero_a
= 0
503 self
.imm
= self
.imm_ok
= 0
504 self
.imm_control
= (0, 0)
505 self
.rdmaskn
= (0, 0)
507 self
.operands
= (0, 0)
509 # Indicates completion of the sub-processes
510 self
.rd_complete
= [False, False]
513 print("Begin parallel test.")
514 yield from self
.operation(5, 2, MicrOp
.OP_ADD
)
516 def operation(self
, a
, b
, op
, inv_a
=0, imm
=0, imm_ok
=0, zero_a
=0,
518 # store data for the operation
519 self
.operands
= (a
, b
)
525 self
.imm_control
= (zero_a
, imm_ok
)
526 self
.rdmaskn
= rdmaskn
528 # Initialize completion flags
529 self
.rd_complete
= [False, False]
531 # trigger operation cycle
532 yield from self
.issue()
534 # check that the sub-processes completed, before the busy_o cycle ended
535 for completion
in self
.rd_complete
:
539 # issue_i starts inactive
540 yield self
.dut
.issue_i
.eq(0)
542 for n
in range(self
.MIN_BUSY_LOW
):
544 # busy_o must remain inactive. It cannot rise on its own.
545 busy_o
= yield self
.dut
.busy_o
548 # activate issue_i to begin the operation cycle
549 yield self
.dut
.issue_i
.eq(1)
551 # at the same time, present the operation
552 yield self
.dut
.oper_i
.insn_type
.eq(self
.op
)
553 yield self
.dut
.oper_i
.invert_in
.eq(self
.inv_a
)
554 yield self
.dut
.oper_i
.imm_data
.data
.eq(self
.imm
)
555 yield self
.dut
.oper_i
.imm_data
.ok
.eq(self
.imm_ok
)
556 yield self
.dut
.oper_i
.zero_a
.eq(self
.zero_a
)
557 rdmaskn
= self
.rdmaskn
[0] |
(self
.rdmaskn
[1] << 1)
558 yield self
.dut
.rdmaskn
.eq(rdmaskn
)
560 # give one cycle for the CompUnit to latch the data
563 # busy_o must keep being low in this cycle, because issue_i was
564 # low on the previous cycle.
565 # It cannot rise on its own.
566 # Also, busy_o and issue_i must never be active at the same time, ever.
567 busy_o
= yield self
.dut
.busy_o
571 yield self
.dut
.issue_i
.eq(0)
573 # deactivate inputs along with issue_i, so we can be sure the data
574 # was latched at the correct cycle
575 # note: rdmaskn must be held, while busy_o is active
576 # TODO: deactivate rdmaskn when the busy_o cycle ends
577 yield self
.dut
.oper_i
.insn_type
.eq(0)
578 yield self
.dut
.oper_i
.invert_in
.eq(0)
579 yield self
.dut
.oper_i
.imm_data
.data
.eq(0)
580 yield self
.dut
.oper_i
.imm_data
.ok
.eq(0)
581 yield self
.dut
.oper_i
.zero_a
.eq(0)
584 # wait for busy_o to lower
585 # timeout after self.MAX_BUSY_WAIT cycles
586 for n
in range(self
.MAX_BUSY_WAIT
):
587 # sample busy_o in the current cycle
588 busy_o
= yield self
.dut
.busy_o
590 # operation cycle ends when busy_o becomes inactive
594 # if busy_o is still active, a timeout has occurred
595 # TODO: Uncomment this, once the test is complete:
599 print("If you are reading this, "
600 "it's because the above test failed, as expected,\n"
601 "with a timeout. It must pass, once the test is complete.")
604 print("If you are reading this, "
605 "it's because the above test unexpectedly passed.")
607 def rd(self
, rd_idx
):
608 # wait for issue_i to rise
610 issue_i
= yield self
.dut
.issue_i
613 # issue_i has not risen yet, so rd must keep low
614 rel
= yield self
.dut
.rd
.rel_o
[rd_idx
]
618 # we do not want rd to rise on an immediate operand
619 # if it is immediate, exit the process
620 # likewise, if the read mask is active
621 # TODO: don't exit the process, monitor rd instead to ensure it
622 # doesn't rise on its own
623 if self
.rdmaskn
[rd_idx
] or self
.imm_control
[rd_idx
]:
624 self
.rd_complete
[rd_idx
] = True
627 # issue_i has risen. rel must rise on the next cycle
628 rel
= yield self
.dut
.rd
.rel_o
[rd_idx
]
631 # stall for additional cycles. Check that rel doesn't fall on its own
632 for n
in range(self
.RD_GO_DELAY
[rd_idx
]):
634 rel
= yield self
.dut
.rd
.rel_o
[rd_idx
]
637 # Before asserting "go", make sure "rel" has risen.
638 # The use of Settle allows "go" to be set combinatorially,
639 # rising on the same cycle as "rel".
641 rel
= yield self
.dut
.rd
.rel_o
[rd_idx
]
644 # assert go for one cycle, passing along the operand value
645 yield self
.dut
.rd
.go_i
[rd_idx
].eq(1)
646 yield self
.dut
.src_i
[rd_idx
].eq(self
.operands
[rd_idx
])
647 # check that the operand was sent to the alu
648 # TODO: Properly check the alu protocol
650 alu_input
= yield self
.dut
.get_in(rd_idx
)
651 assert alu_input
== self
.operands
[rd_idx
]
654 # rel must keep high, since go was inactive in the last cycle
655 rel
= yield self
.dut
.rd
.rel_o
[rd_idx
]
658 # finish the go one-clock pulse
659 yield self
.dut
.rd
.go_i
[rd_idx
].eq(0)
660 yield self
.dut
.src_i
[rd_idx
].eq(0)
663 # rel must have gone low in response to go being high
664 # on the previous cycle
665 rel
= yield self
.dut
.rd
.rel_o
[rd_idx
]
668 self
.rd_complete
[rd_idx
] = True
670 # TODO: check that rel doesn't rise again until the end of the
673 def wr(self
, wr_idx
):
674 # monitor self.dut.wr.req[rd_idx] and sets dut.wr.go[idx] for one cycle
676 # TODO: also when dut.wr.go is set, check the output against the
677 # self.expected_o and assert. use dut.get_out(wr_idx) to do so.
679 def run_simulation(self
, vcd_name
):
681 m
.submodules
.cu
= self
.dut
685 sim
.add_sync_process(wrap(self
.driver()))
686 sim
.add_sync_process(wrap(self
.rd(0)))
687 sim
.add_sync_process(wrap(self
.rd(1)))
688 sim
.add_sync_process(wrap(self
.wr(0)))
689 sim_writer
= sim
.write_vcd(vcd_name
)
694 def test_compunit_regspec2_fsm():
696 inspec
= [('INT', 'data', '0:15'),
697 ('INT', 'shift', '0:15'),
699 outspec
= [('INT', 'data', '0:15'),
702 regspec
= (inspec
, outspec
)
706 dut
= MultiCompUnit(regspec
, alu
, CompFSMOpSubset
)
707 m
.submodules
.cu
= dut
712 # create one operand producer for each input port
713 prod_a
= OperandProducer(sim
, dut
, 0)
714 prod_b
= OperandProducer(sim
, dut
, 1)
715 # create an result consumer for the output port
716 cons
= ResultConsumer(sim
, dut
, 0)
717 sim
.add_sync_process(wrap(scoreboard_sim_fsm(dut
,
720 sim_writer
= sim
.write_vcd('test_compunit_regspec2_fsm.vcd',
721 traces
=[prod_a
.count
,
728 def test_compunit_regspec3():
730 inspec
= [('INT', 'a', '0:15'),
731 ('INT', 'b', '0:15'),
732 ('INT', 'c', '0:15')]
733 outspec
= [('INT', 'o', '0:15'),
736 regspec
= (inspec
, outspec
)
740 dut
= MultiCompUnit(regspec
, alu
, CompALUOpSubset
)
741 m
.submodules
.cu
= dut
746 sim
.add_sync_process(wrap(scoreboard_sim_dummy(dut
)))
747 sim_writer
= sim
.write_vcd('test_compunit_regspec3.vcd')
752 def test_compunit_regspec1():
755 'in': {'color': 'orange'},
756 'out': {'color': 'yellow'},
760 ('operation port', {'color': 'red'}, [
761 'cu_issue_i', 'cu_busy_o',
762 {'comment': 'operation'},
763 ('oper_i_None__insn_type', {'display': 'insn_type'}),
764 ('oper_i_None__invert_in', {'display': 'invert_in'}),
765 ('oper_i_None__imm_data__data[63:0]', {'display': 'data[63:0]'}),
766 ('oper_i_None__imm_data__imm_ok', {'display': 'imm_ok'}),
767 ('oper_i_None__zero_a', {'display': 'zero_a'})]),
768 ('operand 1 port', 'in', [
769 ('cu_rd__rel_o[1:0]', {'bit': 1}),
770 ('cu_rd__go_i[1:0]', {'bit': 1}),
772 ('operand 2 port', 'in', [
773 ('cu_rd__rel_o[1:0]', {'bit': 0}),
774 ('cu_rd__go_i[1:0]', {'bit': 0}),
776 ('result port', 'out', [
777 'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']),
778 ('alu', {'module': 'top.cu.alu'}, [
779 ('prev port', 'in', [
780 'op__insn_type', 'op__invert_i', 'a[15:0]', 'b[15:0]',
781 'valid_i', 'ready_o']),
782 ('next port', 'out', [
783 'alu_o[15:0]', 'valid_o', 'ready_i'])]),
784 ('debug', {'module': 'top'},
785 ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])]
787 write_gtkw("test_compunit_regspec1.gtkw",
788 "test_compunit_regspec1.vcd",
793 inspec
= [('INT', 'a', '0:15'),
794 ('INT', 'b', '0:15')]
795 outspec
= [('INT', 'o', '0:15'),
798 regspec
= (inspec
, outspec
)
802 dut
= MultiCompUnit(regspec
, alu
, CompALUOpSubset
)
803 m
.submodules
.cu
= dut
805 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
806 with
open("test_compunit_regspec1.il", "w") as f
:
812 # create an operation issuer
814 sim
.add_sync_process(wrap(scoreboard_sim(op
)))
815 sim_writer
= sim
.write_vcd('test_compunit_regspec1.vcd',
816 traces
=[op
.producers
[0].count
,
817 op
.producers
[1].count
,
818 op
.consumers
[0].count
])
822 test
= CompUnitParallelTest(dut
)
823 test
.run_simulation("test_compunit_parallel.vcd")
826 if __name__
== '__main__':
829 test_compunit_regspec1()
830 test_compunit_regspec2_fsm()
831 test_compunit_regspec3()