1 """Computation Unit (aka "ALU Manager").
3 Manages a Pipeline or FSM, ensuring that the start and end time are 100%
4 monitored. At no time may the ALU proceed without this module notifying
5 the Dependency Matrices. At no time is a result production "abandoned".
6 This module blocks (indicates busy) starting from when it first receives
7 an opcode until it receives notification that
8 its result(s) have been successfully stored in the regfile(s)
10 Documented at http://libre-soc.org/3d_gpu/architecture/compunit
13 from soc
.experiment
.alu_fsm
import Shifter
, CompFSMOpSubset
14 from soc
.fu
.alu
.alu_input_record
import CompALUOpSubset
15 from soc
.experiment
.alu_hier
import ALU
, DummyALU
16 from soc
.experiment
.compalu_multi
import MultiCompUnit
17 from soc
.decoder
.power_enums
import MicrOp
18 from nmigen
import Module
19 from nmigen
.cli
import rtlil
22 from nmigen
.sim
.cxxsim
import Simulator
, Settle
24 from nmigen
.back
.pysim
import Simulator
, Settle
33 def op_sim_fsm(dut
, a
, b
, direction
):
34 print("op_sim_fsm", a
, b
, direction
)
35 yield dut
.issue_i
.eq(0)
37 yield dut
.src_i
[0].eq(a
)
38 yield dut
.src_i
[1].eq(b
)
39 yield dut
.oper_i
.sdir
.eq(direction
)
40 yield dut
.issue_i
.eq(1)
42 yield dut
.issue_i
.eq(0)
45 yield dut
.rd
.go_i
.eq(0b11)
48 rd_rel_o
= yield dut
.rd
.rel_o
49 print("rd_rel", rd_rel_o
)
52 yield dut
.rd
.go_i
.eq(0)
54 req_rel_o
= yield dut
.wr
.rel_o
55 result
= yield dut
.data_o
56 print("req_rel", req_rel_o
, result
)
58 req_rel_o
= yield dut
.wr
.rel_o
59 result
= yield dut
.data_o
60 print("req_rel", req_rel_o
, result
)
64 yield dut
.wr
.go_i
[0].eq(1)
66 result
= yield dut
.data_o
68 print("result", result
)
69 yield dut
.wr
.go_i
[0].eq(0)
74 def op_sim(dut
, a
, b
, op
, inv_a
=0, imm
=0, imm_ok
=0, zero_a
=0):
75 yield dut
.issue_i
.eq(0)
77 yield dut
.src_i
[0].eq(a
)
78 yield dut
.src_i
[1].eq(b
)
79 yield dut
.oper_i
.insn_type
.eq(op
)
80 yield dut
.oper_i
.invert_in
.eq(inv_a
)
81 yield dut
.oper_i
.imm_data
.imm
.eq(imm
)
82 yield dut
.oper_i
.imm_data
.imm_ok
.eq(imm_ok
)
83 yield dut
.oper_i
.zero_a
.eq(zero_a
)
84 yield dut
.issue_i
.eq(1)
86 yield dut
.issue_i
.eq(0)
88 if not imm_ok
or not zero_a
:
89 yield dut
.rd
.go_i
.eq(0b11)
92 rd_rel_o
= yield dut
.rd
.rel_o
93 print("rd_rel", rd_rel_o
)
96 yield dut
.rd
.go_i
.eq(0)
100 if len(dut
.src_i
) == 3:
101 yield dut
.rd
.go_i
.eq(0b100)
104 rd_rel_o
= yield dut
.rd
.rel_o
105 print("rd_rel", rd_rel_o
)
108 yield dut
.rd
.go_i
.eq(0)
112 req_rel_o
= yield dut
.wr
.rel_o
113 result
= yield dut
.data_o
114 print("req_rel", req_rel_o
, result
)
116 req_rel_o
= yield dut
.wr
.rel_o
117 result
= yield dut
.data_o
118 print("req_rel", req_rel_o
, result
)
122 yield dut
.wr
.go_i
[0].eq(1)
124 result
= yield dut
.data_o
126 print("result", result
)
127 yield dut
.wr
.go_i
[0].eq(0)
132 def scoreboard_sim_fsm(dut
):
133 result
= yield from op_sim_fsm(dut
, 13, 2, 1)
134 assert result
== 3, result
136 result
= yield from op_sim_fsm(dut
, 3, 4, 0)
137 assert result
== 48, result
139 result
= yield from op_sim_fsm(dut
, 21, 0, 0)
140 assert result
== 21, result
143 def scoreboard_sim_dummy(dut
):
144 result
= yield from op_sim(dut
, 5, 2, MicrOp
.OP_NOP
, inv_a
=0,
146 assert result
== 5, result
148 result
= yield from op_sim(dut
, 9, 2, MicrOp
.OP_NOP
, inv_a
=0,
150 assert result
== 9, result
153 def scoreboard_sim(dut
):
154 # zero (no) input operands test
155 result
= yield from op_sim(dut
, 5, 2, MicrOp
.OP_ADD
, zero_a
=1,
159 result
= yield from op_sim(dut
, 5, 2, MicrOp
.OP_ADD
, inv_a
=0,
163 result
= yield from op_sim(dut
, 5, 2, MicrOp
.OP_ADD
)
166 result
= yield from op_sim(dut
, 5, 2, MicrOp
.OP_ADD
, inv_a
=1)
167 assert result
== 65532
169 result
= yield from op_sim(dut
, 5, 2, MicrOp
.OP_ADD
, zero_a
=1)
172 # test combinatorial zero-delay operation
173 # In the test ALU, any operation other than ADD, MUL or SHR
174 # is zero-delay, and do a subtraction.
175 result
= yield from op_sim(dut
, 5, 2, MicrOp
.OP_NOP
)
179 def test_compunit_fsm():
183 dut
= MultiCompUnit(8, alu
, CompFSMOpSubset
)
184 m
.submodules
.cu
= dut
186 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
187 with
open("test_compunit_fsm1.il", "w") as f
:
193 sim
.add_sync_process(wrap(scoreboard_sim_fsm(dut
)))
194 sim_writer
= sim
.write_vcd('test_compunit_fsm1.vcd')
203 dut
= MultiCompUnit(16, alu
, CompALUOpSubset
)
204 m
.submodules
.cu
= dut
206 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
207 with
open("test_compunit1.il", "w") as f
:
213 sim
.add_sync_process(wrap(scoreboard_sim(dut
)))
214 sim_writer
= sim
.write_vcd('test_compunit1.vcd')
219 class CompUnitParallelTest
:
220 def __init__(self
, dut
):
223 # Operation cycle should not take longer than this:
224 self
.MAX_BUSY_WAIT
= 50
226 # Minimum duration in which issue_i will be kept inactive,
227 # during which busy_o must remain low.
228 self
.MIN_BUSY_LOW
= 5
230 # Number of cycles to stall until the assertion of go.
231 # One value, for each port. Can be zero, for no delay.
232 self
.RD_GO_DELAY
= [0, 3]
234 # store common data for the input operation of the processes
237 self
.inv_a
= self
.zero_a
= 0
238 self
.imm
= self
.imm_ok
= 0
239 self
.imm_control
= (0, 0)
240 self
.rdmaskn
= (0, 0)
242 self
.operands
= (0, 0)
244 # Indicates completion of the sub-processes
245 self
.rd_complete
= [False, False]
248 print("Begin parallel test.")
249 yield from self
.operation(5, 2, MicrOp
.OP_ADD
)
251 def operation(self
, a
, b
, op
, inv_a
=0, imm
=0, imm_ok
=0, zero_a
=0,
253 # store data for the operation
254 self
.operands
= (a
, b
)
260 self
.imm_control
= (zero_a
, imm_ok
)
261 self
.rdmaskn
= rdmaskn
263 # Initialize completion flags
264 self
.rd_complete
= [False, False]
266 # trigger operation cycle
267 yield from self
.issue()
269 # check that the sub-processes completed, before the busy_o cycle ended
270 for completion
in self
.rd_complete
:
274 # issue_i starts inactive
275 yield self
.dut
.issue_i
.eq(0)
277 for n
in range(self
.MIN_BUSY_LOW
):
279 # busy_o must remain inactive. It cannot rise on its own.
280 busy_o
= yield self
.dut
.busy_o
283 # activate issue_i to begin the operation cycle
284 yield self
.dut
.issue_i
.eq(1)
286 # at the same time, present the operation
287 yield self
.dut
.oper_i
.insn_type
.eq(self
.op
)
288 yield self
.dut
.oper_i
.invert_in
.eq(self
.inv_a
)
289 yield self
.dut
.oper_i
.imm_data
.imm
.eq(self
.imm
)
290 yield self
.dut
.oper_i
.imm_data
.imm_ok
.eq(self
.imm_ok
)
291 yield self
.dut
.oper_i
.zero_a
.eq(self
.zero_a
)
292 rdmaskn
= self
.rdmaskn
[0] |
(self
.rdmaskn
[1] << 1)
293 yield self
.dut
.rdmaskn
.eq(rdmaskn
)
295 # give one cycle for the CompUnit to latch the data
298 # busy_o must keep being low in this cycle, because issue_i was
299 # low on the previous cycle.
300 # It cannot rise on its own.
301 # Also, busy_o and issue_i must never be active at the same time, ever.
302 busy_o
= yield self
.dut
.busy_o
306 yield self
.dut
.issue_i
.eq(0)
308 # deactivate inputs along with issue_i, so we can be sure the data
309 # was latched at the correct cycle
310 # note: rdmaskn must be held, while busy_o is active
311 # TODO: deactivate rdmaskn when the busy_o cycle ends
312 yield self
.dut
.oper_i
.insn_type
.eq(0)
313 yield self
.dut
.oper_i
.invert_in
.eq(0)
314 yield self
.dut
.oper_i
.imm_data
.imm
.eq(0)
315 yield self
.dut
.oper_i
.imm_data
.imm_ok
.eq(0)
316 yield self
.dut
.oper_i
.zero_a
.eq(0)
319 # wait for busy_o to lower
320 # timeout after self.MAX_BUSY_WAIT cycles
321 for n
in range(self
.MAX_BUSY_WAIT
):
322 # sample busy_o in the current cycle
323 busy_o
= yield self
.dut
.busy_o
325 # operation cycle ends when busy_o becomes inactive
329 # if busy_o is still active, a timeout has occurred
330 # TODO: Uncomment this, once the test is complete:
334 print("If you are reading this, "
335 "it's because the above test failed, as expected,\n"
336 "with a timeout. It must pass, once the test is complete.")
339 print("If you are reading this, "
340 "it's because the above test unexpectedly passed.")
342 def rd(self
, rd_idx
):
343 # wait for issue_i to rise
345 issue_i
= yield self
.dut
.issue_i
348 # issue_i has not risen yet, so rd must keep low
349 rel
= yield self
.dut
.rd
.rel_o
[rd_idx
]
353 # we do not want rd to rise on an immediate operand
354 # if it is immediate, exit the process
355 # likewise, if the read mask is active
356 # TODO: don't exit the process, monitor rd instead to ensure it
357 # doesn't rise on its own
358 if self
.rdmaskn
[rd_idx
] or self
.imm_control
[rd_idx
]:
359 self
.rd_complete
[rd_idx
] = True
362 # issue_i has risen. rel must rise on the next cycle
363 rel
= yield self
.dut
.rd
.rel_o
[rd_idx
]
366 # stall for additional cycles. Check that rel doesn't fall on its own
367 for n
in range(self
.RD_GO_DELAY
[rd_idx
]):
369 rel
= yield self
.dut
.rd
.rel_o
[rd_idx
]
372 # Before asserting "go", make sure "rel" has risen.
373 # The use of Settle allows "go" to be set combinatorially,
374 # rising on the same cycle as "rel".
376 rel
= yield self
.dut
.rd
.rel_o
[rd_idx
]
379 # assert go for one cycle, passing along the operand value
380 yield self
.dut
.rd
.go_i
[rd_idx
].eq(1)
381 yield self
.dut
.src_i
[rd_idx
].eq(self
.operands
[rd_idx
])
382 # check that the operand was sent to the alu
383 # TODO: Properly check the alu protocol
385 alu_input
= yield self
.dut
.get_in(rd_idx
)
386 assert alu_input
== self
.operands
[rd_idx
]
389 # rel must keep high, since go was inactive in the last cycle
390 rel
= yield self
.dut
.rd
.rel_o
[rd_idx
]
393 # finish the go one-clock pulse
394 yield self
.dut
.rd
.go_i
[rd_idx
].eq(0)
395 yield self
.dut
.src_i
[rd_idx
].eq(0)
398 # rel must have gone low in response to go being high
399 # on the previous cycle
400 rel
= yield self
.dut
.rd
.rel_o
[rd_idx
]
403 self
.rd_complete
[rd_idx
] = True
405 # TODO: check that rel doesn't rise again until the end of the
408 def wr(self
, wr_idx
):
409 # monitor self.dut.wr.req[rd_idx] and sets dut.wr.go[idx] for one cycle
411 # TODO: also when dut.wr.go is set, check the output against the
412 # self.expected_o and assert. use dut.get_out(wr_idx) to do so.
414 def run_simulation(self
, vcd_name
):
416 m
.submodules
.cu
= self
.dut
420 sim
.add_sync_process(wrap(self
.driver()))
421 sim
.add_sync_process(wrap(self
.rd(0)))
422 sim
.add_sync_process(wrap(self
.rd(1)))
423 sim
.add_sync_process(wrap(self
.wr(0)))
424 sim_writer
= sim
.write_vcd(vcd_name
)
429 def test_compunit_regspec2_fsm():
431 inspec
= [('INT', 'a', '0:15'),
432 ('INT', 'b', '0:15'),
434 outspec
= [('INT', 'o', '0:15'),
437 regspec
= (inspec
, outspec
)
441 dut
= MultiCompUnit(regspec
, alu
, CompFSMOpSubset
)
442 m
.submodules
.cu
= dut
447 sim
.add_sync_process(wrap(scoreboard_sim_fsm(dut
)))
448 sim_writer
= sim
.write_vcd('test_compunit_regspec2_fsm.vcd')
453 def test_compunit_regspec3():
455 inspec
= [('INT', 'a', '0:15'),
456 ('INT', 'b', '0:15'),
457 ('INT', 'c', '0:15')]
458 outspec
= [('INT', 'o', '0:15'),
461 regspec
= (inspec
, outspec
)
465 dut
= MultiCompUnit(regspec
, alu
, CompALUOpSubset
)
466 m
.submodules
.cu
= dut
471 sim
.add_sync_process(wrap(scoreboard_sim_dummy(dut
)))
472 sim_writer
= sim
.write_vcd('test_compunit_regspec3.vcd')
477 def test_compunit_regspec1():
479 inspec
= [('INT', 'a', '0:15'),
480 ('INT', 'b', '0:15')]
481 outspec
= [('INT', 'o', '0:15'),
484 regspec
= (inspec
, outspec
)
488 dut
= MultiCompUnit(regspec
, alu
, CompALUOpSubset
)
489 m
.submodules
.cu
= dut
491 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
492 with
open("test_compunit_regspec1.il", "w") as f
:
498 sim
.add_sync_process(wrap(scoreboard_sim(dut
)))
499 sim_writer
= sim
.write_vcd('test_compunit_regspec1.vcd')
503 test
= CompUnitParallelTest(dut
)
504 test
.run_simulation("test_compunit_parallel.vcd")
507 if __name__
== '__main__':
510 test_compunit_regspec1()
511 test_compunit_regspec3()