src/soc/experiment/test/test_compldst_multi.py

   1 """Self-contained unit test for the Load/Store CompUnit
   2 """
   3
   4 import unittest
   5 from nmigen import Module
   6 from nmigen.sim import Simulator
   7
   8 from openpower.consts import MSR
   9 from openpower.decoder.power_enums import MicrOp, LDSTMode
  10
  11 from soc.experiment.compldst_multi import LDSTCompUnit
  12 from soc.experiment.pimem import PortInterface
  13 from soc.fu.ldst.pipe_data import LDSTPipeSpec
  14
  15
  16 class OpSim:
  17     def __init__(self, dut):
  18         self.dut = dut
  19
  20     def issue(self, op, zero_a=False, imm=None, update=False,
  21               byterev=True, signext=False,
  22               data_len=2, msr_pr=0):
  23         dut = self.dut
  24         yield dut.oper_i.insn_type.eq(op)
  25         yield dut.oper_i.data_len.eq(data_len)
  26         yield dut.oper_i.zero_a.eq(zero_a)
  27         yield dut.oper_i.byte_reverse.eq(byterev)
  28         yield dut.oper_i.sign_extend.eq(signext)
  29         if imm is not None:
  30             yield dut.oper_i.imm_data.data.eq(imm)
  31             yield dut.oper_i.imm_data.ok.eq(1)
  32         if update:
  33             yield dut.oper_i.ldst_mode.eq(LDSTMode.update)
  34         yield dut.oper_i.msr[MSR.PR].eq(msr_pr)
  35         yield dut.issue_i.eq(1)
  36         yield
  37         yield dut.issue_i.eq(0)
  38         # deactivate decoder inputs along with issue_i, so we can be sure they
  39         # were latched at the correct cycle
  40         yield dut.oper_i.insn_type.eq(0)
  41         yield dut.oper_i.data_len.eq(0)
  42         yield dut.oper_i.zero_a.eq(0)
  43         yield dut.oper_i.byte_reverse.eq(0)
  44         yield dut.oper_i.sign_extend.eq(0)
  45         yield dut.oper_i.imm_data.data.eq(0)
  46         yield dut.oper_i.imm_data.ok.eq(0)
  47         yield dut.oper_i.ldst_mode.eq(LDSTMode.NONE)
  48         yield dut.oper_i.msr[MSR.PR].eq(0)
  49
  50
  51 class TestLDSTCompUnit(unittest.TestCase):
  52
  53     def test_ldst_compunit(self):
  54         m = Module()
  55         pi = PortInterface(name="pi")
  56         regspec = LDSTPipeSpec.regspec
  57         dut = LDSTCompUnit(pi, regspec)
  58         m.submodules.dut = dut
  59         sim = Simulator(m)
  60         sim.add_clock(1e-6)
  61         op = OpSim(dut)
  62
  63         def process():
  64             yield from op.issue(MicrOp.OP_STORE)
  65
  66         sim.add_sync_process(process)
  67         sim_writer = sim.write_vcd("test_ldst_compunit.vcd")
  68         with sim_writer:
  69             sim.run()
  70
  71
  72 if __name__ == '__main__':
  73     unittest.main()