src/soc/experiment/test/test_compldst_multi_mmu_fsm.py

   1 # test case for LOAD / STORE Computation Unit using MMU
   2
   3 from nmigen.back.pysim import Simulator, Delay, Settle, Tick
   4 from nmigen.cli import verilog, rtlil
   5 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
   6 from nmigen.hdl.rec import Record, Layout
   7
   8 from nmutil.latch import SRLatch, latchregister
   9 from nmutil.byterev import byte_reverse
  10 from nmutil.extend import exts
  11 from nmutil.util import wrap
  12 from soc.fu.regspec import RegSpecAPI
  13
  14 from openpower.decoder.power_enums import MicrOp, Function, LDSTMode
  15 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
  16 from openpower.decoder.power_decoder2 import Data
  17 from openpower.consts import MSR
  18
  19 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  20 from soc.experiment.l0_cache import PortInterface
  21 from soc.experiment.pimem import LDSTException
  22 from soc.experiment.compldst_multi import LDSTCompUnit, load, store
  23 from soc.config.test.test_loadstore import TestMemPspec
  24
  25 from soc.experiment.mmu import MMU
  26 from nmutil.util import Display
  27
  28 from soc.config.loadstore import ConfigMemoryPortInterface
  29 from soc.experiment.test import pagetables
  30 from soc.experiment.test.test_wishbone import wb_get
  31
  32 #new unit added to this test case
  33 from soc.fu.mmu.pipe_data import MMUPipeSpec
  34 from soc.fu.mmu.fsm import FSMMMUStage
  35
  36 #for sending instructions to the FSM
  37 from openpower.consts import MSR
  38 from openpower.decoder.power_fields import DecodeFields
  39 from openpower.decoder.power_fieldsn import SignalBitRange
  40 from openpower.decoder.power_decoder2 import decode_spr_num
  41 from openpower.decoder.power_enums import MicrOp
  42
  43 def test_TLBIE(dut):
  44     yield dut.fsm.p.i_data.ctx.op.eq(MicrOp.OP_TLBIE)
  45     yield dut.fsm.p.valid_i.eq(1)
  46     yield
  47     yield dut.fsm.p.valid_i.eq(0)
  48     yield
  49     yield
  50     yield
  51     yield
  52     yield Display("OP_TLBIE test done")
  53
  54 def ldst_sim(dut):
  55     yield dut.mmu.rin.prtbl.eq(0x1000000) # set process table
  56     addr = 0x100e0
  57     data = 0xFF #just a single byte for this test
  58     #data = 0xf553b658ba7e1f51
  59
  60     yield from store(dut, addr, 0, data, 0)
  61     yield
  62     ld_data, data_ok, ld_addr = yield from load(dut, addr, 0, 0)
  63     print(data,data_ok,ld_addr)
  64     assert(ld_data==data)
  65     yield
  66     yield from test_TLBIE(dut)
  67
  68
  69     """
  70     -- not testing dzbz here --
  71     data = 0
  72
  73     print("doing dcbz/store with data 0 .....")
  74     yield from store_debug(dut, addr, 0, data, 0, dcbz=True) #hangs
  75
  76     ld_data, data_ok, ld_addr = yield from load(dut, addr, 0, 0)
  77     print(data,data_ok,ld_addr)
  78     print("ld_data is")
  79     print(ld_data)
  80     assert(ld_data==data)
  81     print("dzbz test passed")
  82     """
  83
  84     dut.stop = True # stop simulation
  85
  86 ########################################
  87
  88
  89 class TestLDSTCompUnitMMUFSM(LDSTCompUnit):
  90
  91     def __init__(self, rwid, pspec):
  92         from soc.experiment.l0_cache import TstL0CacheBuffer
  93         self.l0 = l0 = TstL0CacheBuffer(pspec)
  94         pi = l0.l0.dports[0]
  95         LDSTCompUnit.__init__(self, pi, rwid, 4)
  96
  97     def elaborate(self, platform):
  98         m = LDSTCompUnit.elaborate(self, platform)
  99         m.submodules.l0 = self.l0
 100         # link addr-go direct to rel
 101         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
 102         return m
 103
 104
 105 def test_scoreboard_mmu():
 106
 107     units = {}
 108     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
 109                          imem_ifacetype='bare_wb',
 110                          addr_wid=48,
 111                          mask_wid=8,
 112                          reg_wid=64,
 113                          units=units)
 114
 115     dut = TestLDSTCompUnit(16,pspec)
 116     vl = rtlil.convertMMUFSM(dut, ports=dut.ports())
 117     with open("test_ldst_comp_mmu1.il", "w") as f:
 118         f.write(vl)
 119
 120     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_comp.vcd')
 121
 122 ########################################
 123 class TestLDSTCompUnitRegSpecMMUFSM(LDSTCompUnit):
 124
 125     def __init__(self, pspec):
 126         from soc.experiment.l0_cache import TstL0CacheBuffer
 127         from soc.fu.ldst.pipe_data import LDSTPipeSpec
 128         regspec = LDSTPipeSpec.regspec
 129
 130         # use a LoadStore1 here
 131
 132         cmpi = ConfigMemoryPortInterface(pspec)
 133         self.cmpi = cmpi
 134         ldst = cmpi.pi
 135         self.l0 = ldst
 136
 137         self.mmu = MMU()
 138
 139         pipe_spec = MMUPipeSpec(id_wid=2)
 140         self.fsm = FSMMMUStage(pipe_spec)
 141
 142         self.fsm.set_ldst_interface(ldst)
 143
 144         LDSTCompUnit.__init__(self, ldst.pi, regspec, 4)
 145
 146     def elaborate(self, platform):
 147         m = LDSTCompUnit.elaborate(self, platform)
 148         m.submodules.l0 = self.l0
 149         m.submodules.mmu = self.mmu
 150         m.submodules.fsm = self.fsm
 151         # link addr-go direct to rel
 152         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
 153
 154         # link mmu and dcache together
 155         dcache = self.l0.dcache
 156         mmu = self.mmu
 157         m.d.comb += dcache.m_in.eq(mmu.d_out) # MMUToDCacheType
 158         m.d.comb += mmu.d_in.eq(dcache.m_out) # DCacheToMMUType
 159
 160         return m
 161
 162 def test_scoreboard_regspec_mmufsm():
 163
 164     m = Module()
 165
 166     units = {}
 167     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
 168                          imem_ifacetype='bare_wb',
 169                          addr_wid=48,
 170                          mask_wid=8,
 171                          reg_wid=64,
 172                          units=units)
 173
 174     dut = TestLDSTCompUnitRegSpecMMUFSM(pspec)
 175
 176     m.submodules.dut = dut
 177
 178     sim = Simulator(m)
 179     sim.add_clock(1e-6)
 180
 181     dut.mem = pagetables.test1
 182     dut.stop = False
 183
 184     sim.add_sync_process(wrap(ldst_sim(dut))) # rename ?
 185     sim.add_sync_process(wrap(wb_get(dut)))
 186     with sim.write_vcd('test_scoreboard_regspec_mmufsm.vcd'):
 187         sim.run()
 188
 189
 190 if __name__ == '__main__':
 191     test_scoreboard_regspec_mmufsm()
 192     #only one test for now -- test_scoreboard_mmu()