1 """DCache PortInterface Test
2 starting as a copy to test_ldst_pi.py
5 from nmigen
import (C
, Module
, Signal
, Elaboratable
, Mux
, Cat
, Repl
, Signal
)
6 from nmigen
.cli
import main
7 from nmigen
.cli
import rtlil
8 from nmutil
.mask
import Mask
, masked
9 from nmutil
.util
import Display
10 from random
import randint
, seed
13 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
15 from nmigen
.sim
.cxxsim
import Simulator
, Delay
, Settle
16 from nmutil
.util
import wrap
18 from soc
.config
.test
.test_pi2ls
import pi_ld
, pi_st
, pi_ldst
, pi_dcbz
19 from soc
.config
.test
.test_loadstore
import TestMemPspec
20 from soc
.config
.loadstore
import ConfigMemoryPortInterface
22 from soc
.fu
.ldst
.loadstore
import LoadStore1
23 from soc
.experiment
.mmu
import MMU
25 from nmigen
.compat
.sim
import run_simulation
30 def b(x
): # byte-reverse function
31 return int.from_bytes(x
.to_bytes(8, byteorder
='little'),
32 byteorder
='big', signed
=False)
35 """simulator process for getting memory load requests
42 while True: # wait for dc_valid
50 addr
= (yield wb
.adr
) << 3
52 print (" WB LOOKUP NO entry @ %x, returning zero" % (addr
))
57 store
= (yield wb
.dat_w
)
59 data
= mem
.get(addr
, 0)
60 # note we assume 8-bit sel, here
69 print (" DCACHE set %x mask %x data %x" % (addr
, sel
, res
))
71 data
= mem
.get(addr
, 0)
72 yield wb
.dat_r
.eq(data
)
73 print (" DCACHE get %x data %x" % (addr
, data
))
85 pspec
= TestMemPspec(ldst_ifacetype
='mmu_cache_wb',
88 #disable_cache=True, # hmmm...
94 cmpi
= ConfigMemoryPortInterface(pspec
)
95 m
.submodules
.ldst
= ldst
= cmpi
.pi
96 m
.submodules
.mmu
= mmu
= MMU()
99 l_in
, l_out
= mmu
.l_in
, mmu
.l_out
100 d_in
, d_out
= dcache
.d_in
, dcache
.d_out
101 wb_out
, wb_in
= dcache
.wb_out
, dcache
.wb_in
103 # link mmu and dcache together
104 m
.d
.comb
+= dcache
.m_in
.eq(mmu
.d_out
) # MMUToDCacheType
105 m
.d
.comb
+= mmu
.d_in
.eq(dcache
.m_out
) # DCacheToMMUType
107 # link ldst and MMU together
108 comb
+= l_in
.eq(ldst
.m_out
)
109 comb
+= ldst
.m_in
.eq(l_out
)
113 ### test case for dcbz
115 def _test_dcbz_addr_zero(dut
, mem
):
116 mmu
= dut
.submodules
.mmu
117 pi
= dut
.submodules
.ldst
.pi
121 yield mmu
.rin
.prtbl
.eq(0x1000000) # set process table
126 # size ==, msr_pr TODO
128 yield from pi_dcbz(pi
, addr
, data
, 8, msr_pr
=1)
134 def test_dcbz_addr_zero():
136 m
, cmpi
= setup_mmu()
138 # dcache_load at addr 0
140 0x10000: # PARTITION_TABLE_2
141 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
142 b(0x800000000100000b),
144 0x30000: # RADIX_ROOT_PTE
145 # V = 1 L = 0 NLB = 0x400 NLS = 9
146 b(0x8000000000040009),
148 0x40000: # RADIX_SECOND_LEVEL
149 # V = 1 L = 1 SW = 0 RPN = 0
150 # R = 1 C = 1 ATT = 0 EAA 0x7
151 b(0xc000000000000183),
153 0x1000000: # PROCESS_TABLE_3
154 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
155 b(0x40000000000300ad),
163 sim
.add_sync_process(wrap(_test_dcbz_addr_zero(m
, mem
)))
164 sim
.add_sync_process(wrap(wb_get(cmpi
.wb_bus(), mem
)))
165 with sim
.write_vcd('test_dcbz_addr_zero.vcd'):
168 if __name__
== '__main__':
169 test_dcbz_addr_zero()