1 from nmigen
import (C
, Module
, Signal
, Elaboratable
, Mux
, Cat
, Repl
, Signal
)
2 from nmigen
.cli
import main
3 from nmigen
.cli
import rtlil
4 from nmutil
.mask
import Mask
, masked
5 from nmutil
.util
import Display
6 from random
import randint
, seed
7 from nmigen
.sim
import Simulator
, Delay
, Settle
8 from nmutil
.util
import wrap
10 from soc
.config
.test
.test_pi2ls
import pi_ld
, pi_st
, pi_ldst
, wait_busy
11 #from soc.config.test.test_pi2ls import pi_st_debug
12 from soc
.config
.test
.test_loadstore
import TestMemPspec
13 from soc
.config
.loadstore
import ConfigMemoryPortInterface
15 from soc
.fu
.ldst
.loadstore
import LoadStore1
16 from soc
.experiment
.mmu
import MMU
17 from soc
.experiment
.test
import pagetables
19 from nmigen
.compat
.sim
import run_simulation
20 from random
import random
25 """simulator process for getting memory load requests
32 while True: # wait for dc_valid
40 addr
= (yield wb
.adr
) << 3
42 print (" WB LOOKUP NO entry @ %x, returning zero" % (addr
))
47 store
= (yield wb
.dat_w
)
49 data
= mem
.get(addr
, 0)
50 # note we assume 8-bit sel, here
59 print (" DCACHE set %x mask %x data %x" % (addr
, sel
, res
))
61 data
= mem
.get(addr
, 0)
62 yield wb
.dat_r
.eq(data
)
63 print (" DCACHE get %x data %x" % (addr
, data
))
75 pspec
= TestMemPspec(ldst_ifacetype
='mmu_cache_wb',
78 #disable_cache=True, # hmmm...
84 cmpi
= ConfigMemoryPortInterface(pspec
)
85 m
.submodules
.ldst
= ldst
= cmpi
.pi
86 m
.submodules
.mmu
= mmu
= MMU()
89 l_in
, l_out
= mmu
.l_in
, mmu
.l_out
90 d_in
, d_out
= dcache
.d_in
, dcache
.d_out
91 wb_out
, wb_in
= dcache
.wb_out
, dcache
.wb_in
93 # link mmu and dcache together
94 m
.d
.comb
+= dcache
.m_in
.eq(mmu
.d_out
) # MMUToDCacheType
95 m
.d
.comb
+= mmu
.d_in
.eq(dcache
.m_out
) # DCacheToMMUType
97 # link ldst and MMU together
98 comb
+= l_in
.eq(ldst
.m_out
)
99 comb
+= ldst
.m_in
.eq(l_out
)
103 test_exceptions
= True
105 def _test_loadstore1_invalid(dut
, mem
):
106 mmu
= dut
.submodules
.mmu
107 pi
= dut
.submodules
.ldst
.pi
111 print("=== test invalid ===")
114 ld_data
, exc
= yield from pi_ld(pi
, addr
, 8, msr_pr
=1)
115 print("ld_data",ld_data
,exc
)
117 invalid
= yield pi
.exc_o
.invalid
120 print("=== test invalid done ===")
125 def _test_loadstore1(dut
, mem
):
126 mmu
= dut
.submodules
.mmu
127 pi
= dut
.submodules
.ldst
.pi
131 yield mmu
.rin
.prtbl
.eq(0x1000000) # set process table
135 data
= 0xf553b658ba7e1f51
137 yield from pi_st(pi
, addr
, data
, 8, msr_pr
=1)
140 ld_data
, exc
= yield from pi_ld(pi
, addr
, 8, msr_pr
=1)
141 assert ld_data
== 0xf553b658ba7e1f51
143 ld_data
, exc
= yield from pi_ld(pi
, addr
, 8, msr_pr
=1)
144 assert ld_data
== 0xf553b658ba7e1f51
147 print("do_dcbz ===============")
148 yield from pi_st(pi
, addr
, data
, 8, msr_pr
=1, is_dcbz
=1)
149 print("done_dcbz ===============")
152 ld_data
, exc
= yield from pi_ld(pi
, addr
, 8, msr_pr
=1)
153 print("ld_data after dcbz")
159 print("=== alignment error (ld) ===")
161 ld_data
, exc
= yield from pi_ld(pi
, addr
, 8, msr_pr
=1)
162 alignment
= yield pi
.exc_o
.alignment
163 happened
= yield pi
.exc_o
.happened
169 yield from wait_busy(pi
, debug
="pi_ld_E_alignment_error")
170 # wait is only needed in case of in exception here
171 print("=== alignment error test passed (ld) ===")
173 print("=== alignment error (st) ===")
175 exc
= yield from pi_st(pi
, addr
,0, 8, msr_pr
=1)
176 alignment
= yield pi
.exc_o
.alignment
177 happened
= yield pi
.exc_o
.happened
183 yield from wait_busy(pi
, debug
="pi_st_E_alignment_error")
184 # wait is only needed in case of in exception here
185 print("=== alignment error test passed (st) ===")
186 yield # IMPORTANT: wait one clock cycle after failed st
188 print("=== no error ===")
190 ld_data
, exc
= yield from pi_ld(pi
, addr
, 8, msr_pr
=1)
191 print("ld_data",ld_data
,exc
)
192 print("=== no error done ===")
194 # test read at random addresses
195 for i
in range(0,40):
196 n
= int(random()*0x100000)
197 addr
= 0x10000 + n
*16
198 print("== random addr ==")
199 print("ld[RANDOM]",addr
)
200 ld_data
, exc
= yield from pi_ld(pi
, addr
, 8, msr_pr
=1)
201 print("ld_data[RANDOM]",ld_data
,exc
,addr
)
206 def test_loadstore1():
208 m
, cmpi
= setup_mmu()
210 mem
= pagetables
.test1
216 sim
.add_sync_process(wrap(_test_loadstore1(m
, mem
)))
217 sim
.add_sync_process(wrap(wb_get(cmpi
.wb_bus(), mem
)))
218 with sim
.write_vcd('test_loadstore1.vcd'):
221 def test_loadstore1_invalid():
223 m
, cmpi
= setup_mmu()
231 sim
.add_sync_process(wrap(_test_loadstore1_invalid(m
, mem
)))
232 sim
.add_sync_process(wrap(wb_get(cmpi
.wb_bus(), mem
)))
233 with sim
.write_vcd('test_loadstore1_invalid.vcd'):
236 if __name__
== '__main__':
238 test_loadstore1_invalid()