1 from nmigen
import (C
, Module
, Signal
, Elaboratable
, Mux
, Cat
, Repl
, Signal
)
2 from nmigen
.cli
import main
3 from nmigen
.cli
import rtlil
4 from nmutil
.mask
import Mask
, masked
5 from nmutil
.util
import Display
6 from random
import randint
, seed
7 from nmigen
.sim
import Simulator
, Delay
, Settle
8 from nmutil
.util
import wrap
10 from soc
.config
.test
.test_pi2ls
import pi_ld
, pi_st
, pi_ldst
, wait_busy
11 #from soc.config.test.test_pi2ls import pi_st_debug
12 from soc
.config
.test
.test_loadstore
import TestMemPspec
13 from soc
.config
.loadstore
import ConfigMemoryPortInterface
15 from soc
.fu
.ldst
.loadstore
import LoadStore1
16 from soc
.experiment
.mmu
import MMU
17 from soc
.experiment
.test
import pagetables
19 from nmigen
.compat
.sim
import run_simulation
20 from random
import random
25 """simulator process for getting memory load requests
32 while True: # wait for dc_valid
40 addr
= (yield wb
.adr
) << 3
42 print (" WB LOOKUP NO entry @ %x, returning zero" % (addr
))
47 store
= (yield wb
.dat_w
)
49 data
= mem
.get(addr
, 0)
50 # note we assume 8-bit sel, here
59 print (" DCACHE set %x mask %x data %x" % (addr
, sel
, res
))
61 data
= mem
.get(addr
, 0)
62 yield wb
.dat_r
.eq(data
)
63 print (" DCACHE get %x data %x" % (addr
, data
))
75 pspec
= TestMemPspec(ldst_ifacetype
='mmu_cache_wb',
78 #disable_cache=True, # hmmm...
84 cmpi
= ConfigMemoryPortInterface(pspec
)
85 m
.submodules
.ldst
= ldst
= cmpi
.pi
86 m
.submodules
.mmu
= mmu
= MMU()
89 l_in
, l_out
= mmu
.l_in
, mmu
.l_out
90 d_in
, d_out
= dcache
.d_in
, dcache
.d_out
91 wb_out
, wb_in
= dcache
.wb_out
, dcache
.wb_in
93 # link mmu and dcache together
94 m
.d
.comb
+= dcache
.m_in
.eq(mmu
.d_out
) # MMUToDCacheType
95 m
.d
.comb
+= mmu
.d_in
.eq(dcache
.m_out
) # DCacheToMMUType
97 # link ldst and MMU together
98 comb
+= l_in
.eq(ldst
.m_out
)
99 comb
+= ldst
.m_in
.eq(l_out
)
103 test_exceptions
= False
106 def _test_loadstore1_invalid(dut
, mem
):
107 mmu
= dut
.submodules
.mmu
108 pi
= dut
.submodules
.ldst
.pi
112 print("=== test invalid ===")
115 ld_data
, exc
= yield from pi_ld(pi
, addr
, 8, msr_pr
=1)
116 print("ld_data",ld_data
,exc
)
118 invalid
= yield pi
.exc_o
.invalid
121 print("=== test invalid done ===")
126 def _test_loadstore1(dut
, mem
):
127 mmu
= dut
.submodules
.mmu
128 pi
= dut
.submodules
.ldst
.pi
132 yield mmu
.rin
.prtbl
.eq(0x1000000) # set process table
136 data
= 0xf553b658ba7e1f51
139 yield from pi_st(pi, addr, data, 8, msr_pr=1)
142 ld_data, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
143 assert ld_data == 0xf553b658ba7e1f51
145 ld_data, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
146 assert ld_data == 0xf553b658ba7e1f51
149 print("do_dcbz ===============")
150 yield from pi_st(pi, addr, data, 8, msr_pr=1, is_dcbz=1)
151 print("done_dcbz ===============")
154 ld_data, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
155 print("ld_data after dcbz")
162 print("=== alignment error (ld) ===")
164 ld_data
, exc
= yield from pi_ld(pi
, addr
, 8, msr_pr
=1)
165 alignment
= yield pi
.exc_o
.alignment
166 happened
= yield pi
.exc_o
.happened
172 yield from wait_busy(pi
, debug
="pi_ld_E_alignment_error")
173 # wait is only needed in case of in exception here
174 print("=== alignment error test passed (ld) ===")
176 print("=== alignment error (st) ===")
178 exc
= yield from pi_st(pi
, addr
,0, 8, msr_pr
=1)
179 alignment
= yield pi
.exc_o
.alignment
180 happened
= yield pi
.exc_o
.happened
186 yield from wait_busy(pi
, debug
="pi_st_E_alignment_error")
187 # wait is only needed in case of in exception here
188 print("=== alignment error test passed (st) ===")
189 yield # IMPORTANT: wait one clock cycle after failed st
191 print("=== no error ===")
193 ld_data
, exc
= yield from pi_ld(pi
, addr
, 8, msr_pr
=1)
194 print("ld_data",ld_data
,exc
)
195 print("=== no error done ===")
197 addrs
= [0x456920,0xa7a180,0x299420,0x1d9d60] # known to cause an error
201 print("== RANDOM addr ==")
202 print("ld[RANDOM]",addr
)
203 ld_data
, exc
= yield from pi_ld(pi
, addr
, 8, msr_pr
=1)
204 print("ld_data[RANDOM]",ld_data
,exc
,addr
)
205 if exc
=="wait_ldok_infinite_loop": # break cond for debugging
206 print("wait_ldok_infinite_loop:break",count
)
217 def test_loadstore1():
219 m
, cmpi
= setup_mmu()
221 mem
= pagetables
.test1
227 sim
.add_sync_process(wrap(_test_loadstore1(m
, mem
)))
228 sim
.add_sync_process(wrap(wb_get(cmpi
.wb_bus(), mem
)))
229 with sim
.write_vcd('test_loadstore1.vcd'):
232 def test_loadstore1_invalid():
234 m
, cmpi
= setup_mmu()
242 sim
.add_sync_process(wrap(_test_loadstore1_invalid(m
, mem
)))
243 sim
.add_sync_process(wrap(wb_get(cmpi
.wb_bus(), mem
)))
244 with sim
.write_vcd('test_loadstore1_invalid.vcd'):
247 if __name__
== '__main__':
249 #FIX THIS LATER test_loadstore1_invalid()