1 from nmigen
import Signal
, Const
, Cat
2 from soc
.fu
.alu
.alu_input_record
import CompALUOpSubset
3 from soc
.fu
.pipe_data
import IntegerData
, CommonPipeSpec
4 from ieee754
.fpcommon
.getop
import FPPipeContext
5 from soc
.decoder
.power_decoder2
import Data
8 class ALUInputData(IntegerData
):
9 regspec
= [('INT', 'ra', '0:63'), # RA
10 ('INT', 'rb', '0:63'), # RB/immediate
11 ('XER', 'xer_so', '32'), # XER bit 32: SO
12 ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32
13 def __init__(self
, pspec
):
14 super().__init
__(pspec
, False)
16 self
.a
, self
.b
= self
.ra
, self
.rb
19 class ALUOutputData(IntegerData
):
20 regspec
= [('INT', 'o', '0:63'),
21 ('CR', 'cr_a', '0:3'),
22 ('XER', 'xer_ca', '34,45'), # bit0: ca, bit1: ca32
23 ('XER', 'xer_ov', '33,44'), # bit0: ov, bit1: ov32
24 ('XER', 'xer_so', '32')]
25 def __init__(self
, pspec
):
26 super().__init
__(pspec
, True)
31 class ALUPipeSpec(CommonPipeSpec
):
32 regspec
= (ALUInputData
.regspec
, ALUOutputData
.regspec
)
33 opsubsetkls
= CompALUOpSubset