1 # This stage is intended to handle the gating of carry and overflow
2 # out, summary overflow generation, and updating the condition
4 from soc
.fu
.common_output_stage
import CommonOutputStage
5 from soc
.fu
.bitmanip
.pipe_data
import (BitManipOutputData
,
6 BitManipOutputDataFinal
)
9 class BitManipOutputStage(CommonOutputStage
):
12 return BitManipOutputData(self
.pspec
)
15 return BitManipOutputDataFinal(self
.pspec
)