src/soc/fu/bitmanip/pipe_data.py

   1 from soc.fu.bitmanip.input_record import CompBitManipOpSubset
   2 from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
   3 from soc.fu.alu.pipe_data import ALUOutputData
   4
   5
   6 class BitManipInputData(FUBaseData):
   7     regspec = [
   8         ('INT', 'ra', '0:63'),      # RA
   9         ('INT', 'rb', '0:63'),      # RB
  10         ('INT', 'rc', '0:63'),      # RC
  11         ('XER', 'xer_so', '32'),  # XER bit 32: SO
  12     ]
  13
  14     def __init__(self, pspec):
  15         super().__init__(pspec, False)
  16
  17
  18 # input to bitmanip final stage (common output)
  19 class BitManipOutputData(FUBaseData):
  20     regspec = [
  21         ('INT', 'o', '0:63'),        # RT
  22         ('CR', 'cr_a', '0:3'),
  23         ('XER', 'xer_so', '32'),    # bit0: so
  24     ]
  25
  26     def __init__(self, pspec):
  27         super().__init__(pspec, True)
  28         # convenience
  29         self.cr0 = self.cr_a
  30
  31
  32 # output from bitmanip final stage (common output) - note that XER.so
  33 # is *not* included (the only reason it's in the input is because of CR0)
  34 class BitManipOutputDataFinal(FUBaseData):
  35     regspec = [('INT', 'o', '0:63'),        # RT
  36                ('CR', 'cr_a', '0:3'),
  37                ]
  38
  39     def __init__(self, pspec):
  40         super().__init__(pspec, True)
  41         # convenience
  42         self.cr0 = self.cr_a
  43
  44
  45 class BitManipPipeSpec(CommonPipeSpec):
  46     regspec = (BitManipInputData.regspec, BitManipOutputDataFinal.regspec)
  47     opsubsetkls = CompBitManipOpSubset