src/soc/fu/compunits/test/test_compunit.py

   1 from nmigen import Module, Signal, ResetSignal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_decoder2 import (PowerDecode2)
   8 from soc.decoder.power_enums import Function
   9 from soc.decoder.isa.all import ISA
  10
  11 from soc.experiment.compalu_multi import find_ok  # hack
  12 from soc.config.test.test_loadstore import TestMemPspec
  13
  14
  15 def set_cu_input(cu, idx, data):
  16     rdop = cu.get_in_name(idx)
  17     yield cu.src_i[idx].eq(data)
  18     while True:
  19         rd_rel_o = yield cu.rd.rel[idx]
  20         print("rd_rel %d wait HI" % idx, rd_rel_o, rdop, hex(data))
  21         if rd_rel_o:
  22             break
  23         yield
  24     yield cu.rd.go[idx].eq(1)
  25     while True:
  26         yield
  27         rd_rel_o = yield cu.rd.rel[idx]
  28         if rd_rel_o:
  29             break
  30         print("rd_rel %d wait HI" % idx, rd_rel_o)
  31         yield
  32     yield cu.rd.go[idx].eq(0)
  33     yield cu.src_i[idx].eq(0)
  34
  35
  36 def get_cu_output(cu, idx, code):
  37     wrmask = yield cu.wrmask
  38     wrop = cu.get_out_name(idx)
  39     wrok = cu.get_out(idx)
  40     fname = find_ok(wrok.fields)
  41     wrok = yield getattr(wrok, fname)
  42     print("wr_rel mask", repr(code), idx, wrop, bin(wrmask), fname, wrok)
  43     assert wrmask & (1 << idx), \
  44         "get_cu_output '%s': mask bit %d not set\n" \
  45         "write-operand '%s' Data.ok likely not set (%s)" \
  46         % (code, idx, wrop, hex(wrok))
  47     while True:
  48         wr_relall_o = yield cu.wr.rel
  49         wr_rel_o = yield cu.wr.rel[idx]
  50         print("wr_rel %d wait" % idx, hex(wr_relall_o), wr_rel_o)
  51         if wr_rel_o:
  52             break
  53         yield
  54     yield cu.wr.go[idx].eq(1)
  55     yield Settle()
  56     result = yield cu.dest[idx]
  57     yield
  58     yield cu.wr.go[idx].eq(0)
  59     print("result", repr(code), idx, wrop, wrok, hex(result))
  60
  61     return result
  62
  63
  64 def set_cu_inputs(cu, inp):
  65     print("set_cu_inputs", inp)
  66     for idx, data in inp.items():
  67         yield from set_cu_input(cu, idx, data)
  68     # gets out of sync when checking busy if there is no wait, here.
  69     if len(inp) == 0:
  70         yield  # wait one cycle
  71
  72
  73 def set_operand(cu, dec2, sim):
  74     yield from cu.oper_i.eq_from_execute1(dec2.e)
  75     yield cu.issue_i.eq(1)
  76     yield
  77     yield cu.issue_i.eq(0)
  78     yield
  79
  80
  81 def get_cu_outputs(cu, code):
  82     res = {}
  83     # wait for pipeline to indicate valid.  this because for long
  84     # pipelines (or FSMs) the write mask is only valid at that time.
  85     while True:
  86         valid_o = yield cu.alu.n.valid_o
  87         if valid_o:
  88             break
  89         yield
  90     wrmask = yield cu.wrmask
  91     wr_rel_o = yield cu.wr.rel
  92     print("get_cu_outputs", cu.n_dst, wrmask, wr_rel_o)
  93     # no point waiting (however really should doublecheck wr.rel)
  94     if not wrmask:
  95         return {}
  96     # wait for at least one result
  97     while True:
  98         wr_rel_o = yield cu.wr.rel
  99         if wr_rel_o:
 100             break
 101         yield
 102     for i in range(cu.n_dst):
 103         wr_rel_o = yield cu.wr.rel[i]
 104         if wr_rel_o:
 105             result = yield from get_cu_output(cu, i, code)
 106             wrop = cu.get_out_name(i)
 107             print("output", i, wrop, hex(result))
 108             res[wrop] = result
 109     return res
 110
 111
 112 def get_inp_indexed(cu, inp):
 113     res = {}
 114     for i in range(cu.n_src):
 115         wrop = cu.get_in_name(i)
 116         if wrop in inp:
 117             res[i] = inp[wrop]
 118     return res
 119
 120
 121 def get_l0_mem(l0):  # BLECH!
 122     if hasattr(l0.pimem, 'lsui'):
 123         return l0.pimem.lsui.mem
 124     return l0.pimem.mem.mem
 125
 126
 127 def setup_test_memory(l0, sim):
 128     mem = get_l0_mem(l0)
 129     print("before, init mem", mem.depth, mem.width, mem)
 130     for i in range(mem.depth):
 131         data = sim.mem.ld(i*8, 8, False)
 132         print("init ", i, hex(data))
 133         yield mem._array[i].eq(data)
 134     yield Settle()
 135     for k, v in sim.mem.mem.items():
 136         print("    %6x %016x" % (k, v))
 137     print("before, nmigen mem dump")
 138     for i in range(mem.depth):
 139         actual_mem = yield mem._array[i]
 140         print("    %6i %016x" % (i, actual_mem))
 141
 142
 143 def dump_sim_memory(dut, l0, sim, code):
 144     mem = get_l0_mem(l0)
 145     print("sim mem dump")
 146     for k, v in sim.mem.mem.items():
 147         print("    %6x %016x" % (k, v))
 148     print("nmigen mem dump")
 149     for i in range(mem.depth):
 150         actual_mem = yield mem._array[i]
 151         print("    %6i %016x" % (i, actual_mem))
 152
 153
 154 def check_sim_memory(dut, l0, sim, code):
 155     mem = get_l0_mem(l0)
 156
 157     for i in range(mem.depth):
 158         expected_mem = sim.mem.ld(i*8, 8, False)
 159         actual_mem = yield mem._array[i]
 160         dut.assertEqual(expected_mem, actual_mem,
 161                         "%s %d %x %x" % (code, i,
 162                                          expected_mem, actual_mem))
 163
 164
 165 class TestRunner(FHDLTestCase):
 166     def __init__(self, test_data, fukls, iodef, funit, bigendian):
 167         super().__init__("run_all")
 168         self.test_data = test_data
 169         self.fukls = fukls
 170         self.iodef = iodef
 171         self.funit = funit
 172         self.bigendian = bigendian
 173
 174     def execute(self, cu, l0, instruction, pdecode2, simdec2, test):
 175
 176         program = test.program
 177         print("test", test.name, test.mem)
 178         gen = list(program.generate_instructions())
 179         insncode = program.assembly.splitlines()
 180         instructions = list(zip(gen, insncode))
 181         sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
 182                   test.msr,
 183                   initial_insns=gen, respect_pc=True,
 184                   disassembly=insncode,
 185                   bigendian=self.bigendian)
 186
 187         # initialise memory
 188         if self.funit == Function.LDST:
 189             yield from setup_test_memory(l0, sim)
 190
 191         pc = sim.pc.CIA.value
 192         index = pc//4
 193         msr = sim.msr.value
 194         while True:
 195             print("instr pc", pc)
 196             try:
 197                 yield from sim.setup_one()
 198             except KeyError:  # indicates instruction not in imem: stop
 199                 break
 200             yield Settle()
 201             ins, code = instructions[index]
 202             print("instruction @", index, code)
 203
 204             # ask the decoder to decode this binary data (endian'd)
 205             yield pdecode2.dec.bigendian.eq(self.bigendian)  # le / be?
 206             yield pdecode2.msr.eq(msr)  # set MSR "state"
 207             yield pdecode2.cia.eq(pc)  # set PC "state"
 208             yield instruction.eq(ins)          # raw binary instr.
 209             yield Settle()
 210             # debugging issue with branch
 211             if self.funit == Function.BRANCH:
 212                 lk = yield pdecode2.e.do.lk
 213                 fast_out2 = yield pdecode2.e.write_fast2.data
 214                 fast_out2_ok = yield pdecode2.e.write_fast2.ok
 215                 print("lk:", lk, fast_out2, fast_out2_ok)
 216                 op_lk = yield cu.alu.pipe1.p.data_i.ctx.op.lk
 217                 print("op_lk:", op_lk)
 218                 print(dir(cu.alu.pipe1.n.data_o))
 219             fn_unit = yield pdecode2.e.do.fn_unit
 220             fuval = self.funit.value
 221             self.assertEqual(fn_unit & fuval, fuval)
 222
 223             # set operand and get inputs
 224             yield from set_operand(cu, pdecode2, sim)
 225             # reset read-operand mask
 226             rdmask = pdecode2.rdflags(cu)
 227             #print ("hardcoded rdmask", cu.rdflags(pdecode2.e))
 228             #print ("decoder rdmask", rdmask)
 229             yield cu.rdmaskn.eq(~rdmask)
 230
 231             yield Settle()
 232             iname = yield from self.iodef.get_cu_inputs(pdecode2, sim)
 233             inp = get_inp_indexed(cu, iname)
 234
 235             # reset write-operand mask
 236             for idx in range(cu.n_dst):
 237                 wrok = cu.get_out(idx)
 238                 fname = find_ok(wrok.fields)
 239                 yield getattr(wrok, fname).eq(0)
 240
 241             yield Settle()
 242
 243             # set inputs into CU
 244             rd_rel_o = yield cu.rd.rel
 245             wr_rel_o = yield cu.wr.rel
 246             print("before inputs, rd_rel, wr_rel: ",
 247                   bin(rd_rel_o), bin(wr_rel_o))
 248             assert wr_rel_o == 0, "wr.rel %s must be zero. "\
 249                 "previous instr not written all regs\n"\
 250                 "respec %s" % \
 251                 (bin(wr_rel_o), cu.rwid[1])
 252             yield from set_cu_inputs(cu, inp)
 253             rd_rel_o = yield cu.rd.rel
 254             wr_rel_o = yield cu.wr.rel
 255             wrmask = yield cu.wrmask
 256             print("after inputs, rd_rel, wr_rel, wrmask: ",
 257                   bin(rd_rel_o), bin(wr_rel_o), bin(wrmask))
 258
 259             # call simulated operation
 260             yield from sim.execute_one()
 261             yield Settle()
 262             pc = sim.pc.CIA.value
 263             index = pc//4
 264             msr = sim.msr.value
 265
 266             # get all outputs (one by one, just "because")
 267             res = yield from get_cu_outputs(cu, code)
 268             wrmask = yield cu.wrmask
 269             rd_rel_o = yield cu.rd.rel
 270             wr_rel_o = yield cu.wr.rel
 271             print("after got outputs, rd_rel, wr_rel, wrmask: ",
 272                   bin(rd_rel_o), bin(wr_rel_o), bin(wrmask))
 273
 274             # wait for busy to go low
 275             while True:
 276                 busy_o = yield cu.busy_o
 277                 print("busy", busy_o)
 278                 if not busy_o:
 279                     break
 280                 yield
 281
 282             # reset read-mask.  IMPORTANT when there are no operands
 283             yield cu.rdmaskn.eq(0)
 284             yield
 285
 286             # debugging issue with branch
 287             if self.funit == Function.BRANCH:
 288                 lr = yield cu.alu.pipe1.n.data_o.lr.data
 289                 lr_ok = yield cu.alu.pipe1.n.data_o.lr.ok
 290                 print("lr:", hex(lr), lr_ok)
 291
 292             if self.funit == Function.LDST:
 293                 yield from dump_sim_memory(self, l0, sim, code)
 294
 295             # sigh.  hard-coded.  test memory
 296             if self.funit == Function.LDST:
 297                 yield from check_sim_memory(self, l0, sim, code)
 298                 yield from self.iodef.check_cu_outputs(res, pdecode2,
 299                                                        sim, cu,
 300                                                        code)
 301             else:
 302                 yield from self.iodef.check_cu_outputs(res, pdecode2,
 303                                                        sim, cu.alu,
 304                                                        code)
 305
 306     def run_all(self):
 307         m = Module()
 308         comb = m.d.comb
 309         instruction = Signal(32)
 310
 311         pdecode = create_pdecode()
 312         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 313
 314         # copy of the decoder for simulator
 315         simdec = create_pdecode()
 316         simdec2 = PowerDecode2(simdec)
 317         m.submodules.simdec2 = simdec2  # pain in the neck
 318
 319         if self.funit == Function.LDST:
 320             from soc.experiment.l0_cache import TstL0CacheBuffer
 321             pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
 322                                  addr_wid=48,
 323                                  mask_wid=8,
 324                                  reg_wid=64)
 325             m.submodules.l0 = l0 = TstL0CacheBuffer(pspec, n_units=1)
 326             pi = l0.l0.dports[0]
 327             m.submodules.cu = cu = self.fukls(pi, idx=0, awid=3)
 328             m.d.comb += cu.ad.go.eq(cu.ad.rel)  # link addr-go direct to rel
 329             m.d.comb += cu.st.go.eq(cu.st.rel)  # link store-go direct to rel
 330         else:
 331             m.submodules.cu = cu = self.fukls(0)
 332             l0 = None
 333
 334         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 335         sim = Simulator(m)
 336
 337         sim.add_clock(1e-6)
 338
 339         def process():
 340             yield cu.issue_i.eq(0)
 341             yield
 342
 343             for test in self.test_data:
 344                 print(test.name)
 345                 with self.subTest(test.name):
 346                     yield from self.execute(cu, l0, instruction,
 347                                             pdecode2, simdec2,
 348                                             test)
 349
 350         sim.add_sync_process(process)
 351
 352         name = self.funit.name.lower()
 353         with sim.write_vcd("%s_simulator.vcd" % name,
 354                            traces=[]):
 355             sim.run()