src/soc/fu/compunits/test/test_compunit.py

   1 from nmigen import Module, Signal, ResetSignal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_decoder2 import (PowerDecode2)
   8 from soc.decoder.power_enums import Function
   9 from soc.decoder.isa.all import ISA
  10
  11 from soc.experiment.compalu_multi import find_ok  # hack
  12 from soc.config.test.test_loadstore import TestMemPspec
  13
  14
  15 def set_cu_input(cu, idx, data):
  16     rdop = cu.get_in_name(idx)
  17     yield cu.src_i[idx].eq(data)
  18     while True:
  19         rd_rel_o = yield cu.rd.rel[idx]
  20         print("rd_rel %d wait HI" % idx, rd_rel_o, rdop, hex(data))
  21         if rd_rel_o:
  22             break
  23         yield
  24     yield cu.rd.go[idx].eq(1)
  25     while True:
  26         yield
  27         rd_rel_o = yield cu.rd.rel[idx]
  28         if rd_rel_o:
  29             break
  30         print("rd_rel %d wait HI" % idx, rd_rel_o)
  31         yield
  32     yield cu.rd.go[idx].eq(0)
  33     yield cu.src_i[idx].eq(0)
  34
  35
  36 def get_cu_output(cu, idx, code):
  37     wrmask = yield cu.wrmask
  38     wrop = cu.get_out_name(idx)
  39     wrok = cu.get_out(idx)
  40     fname = find_ok(wrok.fields)
  41     wrok = yield getattr(wrok, fname)
  42     print("wr_rel mask", repr(code), idx, wrop, bin(wrmask), fname, wrok)
  43     assert wrmask & (1 << idx), \
  44         "get_cu_output '%s': mask bit %d not set\n" \
  45         "write-operand '%s' Data.ok likely not set (%s)" \
  46         % (code, idx, wrop, hex(wrok))
  47     while True:
  48         wr_relall_o = yield cu.wr.rel
  49         wr_rel_o = yield cu.wr.rel[idx]
  50         print("wr_rel %d wait" % idx, hex(wr_relall_o), wr_rel_o)
  51         if wr_rel_o:
  52             break
  53         yield
  54     yield cu.wr.go[idx].eq(1)
  55     yield Settle()
  56     result = yield cu.dest[idx]
  57     yield
  58     yield cu.wr.go[idx].eq(0)
  59     print("result", repr(code), idx, wrop, wrok, hex(result))
  60
  61     return result
  62
  63
  64 def set_cu_inputs(cu, inp):
  65     print("set_cu_inputs", inp)
  66     for idx, data in inp.items():
  67         yield from set_cu_input(cu, idx, data)
  68     # gets out of sync when checking busy if there is no wait, here.
  69     if len(inp) == 0:
  70         yield  # wait one cycle
  71
  72
  73 def set_operand(cu, dec2, sim):
  74     yield from cu.oper_i.eq_from_execute1(dec2.e)
  75     yield cu.issue_i.eq(1)
  76     yield
  77     yield cu.issue_i.eq(0)
  78     yield
  79
  80
  81 def get_cu_outputs(cu, code):
  82     res = {}
  83     wrmask = yield cu.wrmask
  84     wr_rel_o = yield cu.wr.rel
  85     print("get_cu_outputs", cu.n_dst, wrmask, wr_rel_o)
  86     # no point waiting (however really should doublecheck wr.rel)
  87     if not wrmask:
  88         return {}
  89     # wait for at least one result
  90     while True:
  91         wr_rel_o = yield cu.wr.rel
  92         if wr_rel_o:
  93             break
  94         yield
  95     for i in range(cu.n_dst):
  96         wr_rel_o = yield cu.wr.rel[i]
  97         if wr_rel_o:
  98             result = yield from get_cu_output(cu, i, code)
  99             wrop = cu.get_out_name(i)
 100             print("output", i, wrop, hex(result))
 101             res[wrop] = result
 102     return res
 103
 104
 105 def get_inp_indexed(cu, inp):
 106     res = {}
 107     for i in range(cu.n_src):
 108         wrop = cu.get_in_name(i)
 109         if wrop in inp:
 110             res[i] = inp[wrop]
 111     return res
 112
 113
 114 def get_l0_mem(l0):  # BLECH!
 115     if hasattr(l0.pimem, 'lsui'):
 116         return l0.pimem.lsui.mem
 117     return l0.pimem.mem.mem
 118
 119
 120 def setup_test_memory(l0, sim):
 121     mem = get_l0_mem(l0)
 122     print("before, init mem", mem.depth, mem.width, mem)
 123     for i in range(mem.depth):
 124         data = sim.mem.ld(i*8, 8, False)
 125         print("init ", i, hex(data))
 126         yield mem._array[i].eq(data)
 127     yield Settle()
 128     for k, v in sim.mem.mem.items():
 129         print("    %6x %016x" % (k, v))
 130     print("before, nmigen mem dump")
 131     for i in range(mem.depth):
 132         actual_mem = yield mem._array[i]
 133         print("    %6i %016x" % (i, actual_mem))
 134
 135
 136 def dump_sim_memory(dut, l0, sim, code):
 137     mem = get_l0_mem(l0)
 138     print("sim mem dump")
 139     for k, v in sim.mem.mem.items():
 140         print("    %6x %016x" % (k, v))
 141     print("nmigen mem dump")
 142     for i in range(mem.depth):
 143         actual_mem = yield mem._array[i]
 144         print("    %6i %016x" % (i, actual_mem))
 145
 146
 147 def check_sim_memory(dut, l0, sim, code):
 148     mem = get_l0_mem(l0)
 149
 150     for i in range(mem.depth):
 151         expected_mem = sim.mem.ld(i*8, 8, False)
 152         actual_mem = yield mem._array[i]
 153         dut.assertEqual(expected_mem, actual_mem,
 154                         "%s %d %x %x" % (code, i,
 155                                          expected_mem, actual_mem))
 156
 157
 158 class TestRunner(FHDLTestCase):
 159     def __init__(self, test_data, fukls, iodef, funit, bigendian):
 160         super().__init__("run_all")
 161         self.test_data = test_data
 162         self.fukls = fukls
 163         self.iodef = iodef
 164         self.funit = funit
 165         self.bigendian = bigendian
 166
 167     def run_all(self):
 168         m = Module()
 169         comb = m.d.comb
 170         instruction = Signal(32)
 171
 172         pdecode = create_pdecode()
 173         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 174
 175         # copy of the decoder for simulator
 176         simdec = create_pdecode()
 177         simdec2 = PowerDecode2(simdec)
 178         m.submodules.simdec2 = simdec2  # pain in the neck
 179
 180         if self.funit == Function.LDST:
 181             from soc.experiment.l0_cache import TstL0CacheBuffer
 182             pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
 183                                  addr_wid=48,
 184                                  mask_wid=8,
 185                                  reg_wid=64)
 186             m.submodules.l0 = l0 = TstL0CacheBuffer(pspec, n_units=1)
 187             pi = l0.l0.dports[0]
 188             m.submodules.cu = cu = self.fukls(pi, idx=0, awid=3)
 189             m.d.comb += cu.ad.go.eq(cu.ad.rel)  # link addr-go direct to rel
 190             m.d.comb += cu.st.go.eq(cu.st.rel)  # link store-go direct to rel
 191         else:
 192             m.submodules.cu = cu = self.fukls(0)
 193
 194         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 195         sim = Simulator(m)
 196
 197         sim.add_clock(1e-6)
 198
 199         def process():
 200             yield cu.issue_i.eq(0)
 201             yield
 202
 203             for test in self.test_data:
 204                 print(test.name)
 205                 program = test.program
 206                 self.subTest(test.name)
 207                 print("test", test.name, test.mem)
 208                 gen = list(program.generate_instructions())
 209                 insncode = program.assembly.splitlines()
 210                 instructions = list(zip(gen, insncode))
 211                 sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
 212                           test.msr,
 213                           initial_insns=gen, respect_pc=True,
 214                           disassembly=insncode,
 215                           bigendian=self.bigendian)
 216
 217                 # initialise memory
 218                 if self.funit == Function.LDST:
 219                     yield from setup_test_memory(l0, sim)
 220
 221                 pc = sim.pc.CIA.value
 222                 index = pc//4
 223                 msr = sim.msr.value
 224                 while True:
 225                     print("instr pc", pc)
 226                     try:
 227                         yield from sim.setup_one()
 228                     except KeyError:  # indicates instruction not in imem: stop
 229                         break
 230                     yield Settle()
 231                     ins, code = instructions[index]
 232                     print("instruction @", index, code)
 233
 234                     # ask the decoder to decode this binary data (endian'd)
 235                     yield pdecode2.dec.bigendian.eq(self.bigendian)  # le / be?
 236                     yield pdecode2.msr.eq(msr)  # set MSR "state"
 237                     yield pdecode2.cia.eq(pc)  # set PC "state"
 238                     yield instruction.eq(ins)          # raw binary instr.
 239                     yield Settle()
 240                     # debugging issue with branch
 241                     if self.funit == Function.BRANCH:
 242                         lk = yield pdecode2.e.do.lk
 243                         fast_out2 = yield pdecode2.e.write_fast2.data
 244                         fast_out2_ok = yield pdecode2.e.write_fast2.ok
 245                         print("lk:", lk, fast_out2, fast_out2_ok)
 246                         op_lk = yield cu.alu.pipe1.p.data_i.ctx.op.lk
 247                         print("op_lk:", op_lk)
 248                         print(dir(cu.alu.pipe1.n.data_o))
 249                     fn_unit = yield pdecode2.e.do.fn_unit
 250                     fuval = self.funit.value
 251                     self.assertEqual(fn_unit & fuval, fuval)
 252
 253                     # set operand and get inputs
 254                     yield from set_operand(cu, pdecode2, sim)
 255                     # reset read-operand mask
 256                     rdmask = pdecode2.rdflags(cu)
 257                     #print ("hardcoded rdmask", cu.rdflags(pdecode2.e))
 258                     #print ("decoder rdmask", rdmask)
 259                     yield cu.rdmaskn.eq(~rdmask)
 260
 261                     yield Settle()
 262                     iname = yield from self.iodef.get_cu_inputs(pdecode2, sim)
 263                     inp = get_inp_indexed(cu, iname)
 264
 265                     # reset write-operand mask
 266                     for idx in range(cu.n_dst):
 267                         wrok = cu.get_out(idx)
 268                         fname = find_ok(wrok.fields)
 269                         yield getattr(wrok, fname).eq(0)
 270
 271                     yield Settle()
 272
 273                     # set inputs into CU
 274                     rd_rel_o = yield cu.rd.rel
 275                     wr_rel_o = yield cu.wr.rel
 276                     print("before inputs, rd_rel, wr_rel: ",
 277                           bin(rd_rel_o), bin(wr_rel_o))
 278                     assert wr_rel_o == 0, "wr.rel %s must be zero. "\
 279                         "previous instr not written all regs\n"\
 280                         "respec %s" % \
 281                         (bin(wr_rel_o), cu.rwid[1])
 282                     yield from set_cu_inputs(cu, inp)
 283                     rd_rel_o = yield cu.rd.rel
 284                     wr_rel_o = yield cu.wr.rel
 285                     wrmask = yield cu.wrmask
 286                     print("after inputs, rd_rel, wr_rel, wrmask: ",
 287                           bin(rd_rel_o), bin(wr_rel_o), bin(wrmask))
 288
 289                     # call simulated operation
 290                     yield from sim.execute_one()
 291                     yield Settle()
 292                     pc = sim.pc.CIA.value
 293                     index = pc//4
 294                     msr = sim.msr.value
 295
 296                     # get all outputs (one by one, just "because")
 297                     res = yield from get_cu_outputs(cu, code)
 298                     wrmask = yield cu.wrmask
 299                     rd_rel_o = yield cu.rd.rel
 300                     wr_rel_o = yield cu.wr.rel
 301                     print("after got outputs, rd_rel, wr_rel, wrmask: ",
 302                           bin(rd_rel_o), bin(wr_rel_o), bin(wrmask))
 303
 304                     # reset read-mask.  IMPORTANT when there are no operands
 305                     yield cu.rdmaskn.eq(0)
 306
 307                     # wait for busy to go low
 308                     while True:
 309                         busy_o = yield cu.busy_o
 310                         print("busy", busy_o)
 311                         if not busy_o:
 312                             break
 313                         yield
 314                     yield
 315
 316                     # debugging issue with branch
 317                     if self.funit == Function.BRANCH:
 318                         lr = yield cu.alu.pipe1.n.data_o.lr.data
 319                         lr_ok = yield cu.alu.pipe1.n.data_o.lr.ok
 320                         print("lr:", hex(lr), lr_ok)
 321
 322                     if self.funit == Function.LDST:
 323                         yield from dump_sim_memory(self, l0, sim, code)
 324
 325                     # sigh.  hard-coded.  test memory
 326                     if self.funit == Function.LDST:
 327                         yield from check_sim_memory(self, l0, sim, code)
 328                         yield from self.iodef.check_cu_outputs(res, pdecode2,
 329                                                                sim, cu,
 330                                                                code)
 331                     else:
 332                         yield from self.iodef.check_cu_outputs(res, pdecode2,
 333                                                                sim, cu.alu,
 334                                                                code)
 335
 336         sim.add_sync_process(process)
 337
 338         name = self.funit.name.lower()
 339         with sim.write_vcd("%s_simulator.vcd" % name,
 340                            traces=[]):
 341             sim.run()