src/soc/fu/cr/pipe_data.py

   1 from nmigen import Signal, Const
   2 from ieee754.fpcommon.getop import FPPipeContext
   3 from soc.fu.pipe_data import IntegerData, CommonPipeSpec
   4 from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
   5
   6
   7 class CRInputData(IntegerData):
   8     regspec = [('INT', 'a', '0:63'),      # 64 bit range
   9                ('CR', 'full_cr', '0:31'), # 32 bit range
  10                ('CR', 'cr_a', '0:3'),     # 4 bit range
  11                ('CR', 'cr_b', '0:3'),     # 4 bit range
  12                ('CR', 'cr_c', '0:3')]     # 4 bit range
  13     def __init__(self, pspec):
  14         super().__init__(pspec)
  15         self.a = Signal(64, reset_less=True) # RA
  16         self.full_cr = Signal(32, reset_less=True) # full CR in
  17         self.cr_a = Signal(4, reset_less=True)
  18         self.cr_b = Signal(4, reset_less=True)
  19         self.cr_c = Signal(4, reset_less=True) # needed for CR_OP partial update
  20
  21     def __iter__(self):
  22         yield from super().__iter__()
  23         yield self.a
  24         yield self.full_cr
  25         yield self.cr_a
  26         yield self.cr_b
  27         yield self.cr_c
  28
  29     def eq(self, i):
  30         lst = super().eq(i)
  31         return lst + [self.a.eq(i.a),
  32                       self.full_cr.eq(i.full_cr),
  33                       self.cr_a.eq(i.cr_a),
  34                       self.cr_b.eq(i.cr_b),
  35                       self.cr_c.eq(i.cr_c)]
  36
  37
  38 class CROutputData(IntegerData):
  39     regspec = [('INT', 'o', '0:63'),      # 64 bit range
  40                ('CR', 'full_cr', '0:31'), # 32 bit range
  41                ('CR', 'cr_o', '0:3')]     # 4 bit range
  42     def __init__(self, pspec):
  43         super().__init__(pspec)
  44         self.o = Signal(64, reset_less=True) # RA
  45         self.full_cr = Signal(32, reset_less=True, name="cr_out") # CR in
  46         self.cr_o = Signal(4, reset_less=True)
  47
  48     def __iter__(self):
  49         yield from super().__iter__()
  50         yield self.o
  51         yield self.full_cr
  52         yield self.cr_o
  53
  54     def eq(self, i):
  55         lst = super().eq(i)
  56         return lst + [self.o.eq(i.o),
  57                       self.full_cr.eq(i.full_cr),
  58                       self.cr_o.eq(i.cr_o)]
  59
  60 # TODO: replace CompALUOpSubset with CompCROpSubset
  61 class CRPipeSpec(CommonPipeSpec):
  62     regspec = (CRInputData.regspec, CROutputData.regspec)
  63     opsubsetkls = CompALUOpSubset