1 from nmigen
import Signal
, Const
2 from soc
.fu
.pipe_data
import IntegerData
3 from soc
.fu
.alu
.pipe_data
import ALUOutputData
, CommonPipeSpec
4 from soc
.fu
.alu
.pipe_data
import ALUInputData
# TODO: check this
5 from soc
.fu
.logical
.logical_input_record
import CompLogicalOpSubset
8 class DivPipeSpec(CommonPipeSpec
):
9 regspec
= (ALUInputData
.regspec
, ALUOutputData
.regspec
)
10 opsubsetkls
= CompLogicalOpSubset