src/soc/fu/div/pipe_data.py

   1 from nmigen import Signal, Const
   2 from soc.fu.pipe_data import IntegerData
   3 from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec
   4 from soc.fu.logical.logical_input_record import CompLogicalOpSubset
   5 from ieee754.div_rem_sqrt_rsqrt.core import (
   6     DivPipeCoreConfig, DivPipeCoreInputData, DP,
   7     DivPipeCoreInterstageData, DivPipeCoreOutputData)
   8
   9
  10 class DIVInputData(IntegerData):
  11     regspec = [('INT', 'ra', '0:63'), # RA
  12                ('INT', 'rb', '0:63'), # RB/immediate
  13                ('XER', 'xer_so', '32'),] # XER bit 32: SO
  14     def __init__(self, pspec):
  15         super().__init__(pspec, False)
  16         # convenience
  17         self.a, self.b = self.ra, self.rb
  18
  19
  20 class DIVPipeSpec(CommonPipeSpec):
  21     regspec = (DIVInputData.regspec, ALUOutputData.regspec)
  22     opsubsetkls = CompLogicalOpSubset
  23     core_config = DivPipeCoreConfig(
  24         bit_width=64,
  25         fract_width=64,
  26         log2_radix=1,
  27         supported=[DP.UDivRem]
  28     )
  29
  30
  31 class CoreBaseData(DIVInputData):
  32     def __init__(self, pspec, core_data_class):
  33         super().__init__(pspec)
  34         self.core = core_data_class(pspec.core_config)
  35         self.divisor_neg = Signal(reset_less=True)
  36         self.dividend_neg = Signal(reset_less=True)
  37         self.div_by_zero = Signal(reset_less=True)
  38
  39         # set if an overflow for divide extended instructions is detected
  40         # because `abs_dividend >= abs_divisor` for the appropriate bit width;
  41         # 0 if the instruction is not a divide extended instruction
  42         self.dive_abs_ov32 = Signal(reset_less=True)
  43         self.dive_abs_ov64 = Signal(reset_less=True)
  44
  45     def __iter__(self):
  46         yield from super().__iter__()
  47         yield from self.core.__iter__(self)
  48         yield self.divisor_neg
  49         yield self.dividend_neg
  50
  51     def eq(self, rhs):
  52         return self.eq_without_core(rhs) + self.core.eq(rhs.core)
  53
  54     def eq_without_core(self, rhs):
  55         return super().eq(rhs) + \
  56             [self.divisor_neg.eq(rhs.divisor_neg),
  57              self.dividend_neg.eq(rhs.dividend_neg)]
  58
  59
  60 class CoreInputData(CoreBaseData):
  61     def __init__(self, pspec):
  62         super().__init__(pspec, DivPipeCoreInputData)
  63
  64
  65 class CoreInterstageData(CoreBaseData):
  66     def __init__(self, pspec):
  67         super().__init__(pspec, DivPipeCoreInterstageData)
  68
  69
  70 class CoreOutputData(CoreBaseData):
  71     def __init__(self, pspec):
  72         super().__init__(pspec, DivPipeCoreOutputData)