start adding FSMDivCore*
[soc.git] / src / soc / fu / div / pipeline.py
1 from nmutil.singlepipe import ControlBase
2 from nmutil.pipemodbase import PipeModBaseChain
3 from soc.fu.mul.output_stage import DivMulOutputStage
4 from soc.fu.div.input_stage import DivMulInputStage
5 from soc.fu.div.output_stage import DivOutputStage
6 from soc.fu.div.setup_stage import DivSetupStage
7 from soc.fu.div.core_stages import (DivCoreSetupStage, DivCoreCalculateStage,
8 DivCoreFinalStage)
9
10
11 class DivStagesStart(PipeModBaseChain):
12 def get_chain(self):
13 alu_input = DivMulInputStage(self.pspec)
14 div_setup = DivSetupStage(self.pspec)
15 core_setup = DivCoreSetupStage(self.pspec)
16 return [alu_input, div_setup, core_setup]
17
18
19 class DivStagesMiddle(PipeModBaseChain):
20 def __init__(self, pspec, stage_start_index, stage_end_index):
21 self.stage_start_index = stage_start_index
22 self.stage_end_index = stage_end_index
23 super().__init__(pspec)
24
25 def get_chain(self):
26 stages = []
27 for index in range(self.stage_start_index, self.stage_end_index):
28 stages.append(DivCoreCalculateStage(self.pspec, index))
29 return stages
30
31
32 class DivStagesEnd(PipeModBaseChain):
33 def get_chain(self):
34 core_final = DivCoreFinalStage(self.pspec)
35 div_out = DivOutputStage(self.pspec)
36 alu_out = DivMulOutputStage(self.pspec)
37 self.div_out = div_out # debugging - bug #425
38 return [core_final, div_out, alu_out]
39
40
41 class DivBasePipe(ControlBase):
42 def __init__(self, pspec, compute_steps_per_stage=4):
43 ControlBase.__init__(self)
44 self.pspec = pspec
45 self.pipe_start = DivStagesStart(pspec)
46 compute_steps = pspec.core_config.n_stages
47 self.pipe_middles = []
48 for start in range(0, compute_steps, compute_steps_per_stage):
49 end = min(start + compute_steps_per_stage, compute_steps)
50 self.pipe_middles.append(DivStagesMiddle(pspec, start, end))
51 self.pipe_end = DivStagesEnd(pspec)
52 self._eqs = self.connect([self.pipe_start,
53 *self.pipe_middles,
54 self.pipe_end])
55
56 def elaborate(self, platform):
57 m = ControlBase.elaborate(self, platform)
58 m.submodules.pipe_start = self.pipe_start
59 for i in self.pipe_middles:
60 name = f"pipe_{i.stage_start_index}_to_{i.stage_end_index}"
61 setattr(m.submodules, name, i)
62 m.submodules.pipe_end = self.pipe_end
63 m.d.comb += self._eqs
64 return m