src/soc/fu/div/setup_stage.py

   1 # This stage is the setup stage that converts the inputs
   2 # into the values expected by DivPipeCore
   3
   4 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
   5 from nmutil.pipemodbase import PipeModBase
   6 from soc.fu.div.pipe_data import DIVInputData
   7 from soc.fu.alu.pipe_data import ALUOutputData
   8 from ieee754.part.partsig import PartitionedSignal
   9 from soc.decoder.power_enums import InternalOp
  10
  11 from soc.decoder.power_fields import DecodeFields
  12 from soc.decoder.power_fieldsn import SignalBitRange
  13 from soc.fu.div.pipe_data import CoreInputData
  14 from ieee754.div_rem_sqrt_rsqrt.core import DivPipeCoreOperation
  15 from nmutil.util import eq32
  16
  17
  18 class DivSetupStage(PipeModBase):
  19     def __init__(self, pspec):
  20         super().__init__(pspec, "setup_stage")
  21         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
  22         self.fields.create_specs()
  23
  24     def ispec(self):
  25         return DIVInputData(self.pspec)
  26
  27     def ospec(self):
  28         return CoreInputData(self.pspec)
  29
  30     def elaborate(self, platform):
  31         m = Module()
  32         comb = m.d.comb
  33         # convenience variables
  34         op, a, b = self.i.ctx.op, self.i.a, self.i.b
  35         core_o = self.o.core
  36         dividend_neg_o = self.o.dividend_neg
  37         divisor_neg_o = self.o.divisor_neg
  38         dividend_o = core_o.dividend
  39         divisor_o = core_o.divisor_radicand
  40
  41         # set operation to unsigned div/remainder
  42         comb += core_o.operation.eq(int(DivPipeCoreOperation.UDivRem))
  43
  44         # work out if a/b are negative (check 32-bit / signed)
  45         comb += dividend_neg_o.eq(Mux(op.is_32bit, a[31], a[63]) & op.is_signed)
  46         comb += divisor_neg_o.eq(Mux(op.is_32bit, b[31], b[63]) & op.is_signed)
  47
  48         # negation of a 64-bit value produces the same lower 32-bit
  49         # result as negation of just the lower 32-bits, so we don't
  50         # need to do anything special before negating
  51         abs_dor = Signal(64, reset_less=True) # absolute of divisor
  52         abs_dend = Signal(64, reset_less=True) # absolute of dividend
  53         comb += abs_dor.eq(Mux(divisor_neg_o, -b, b))
  54         comb += abs_dend.eq(Mux(dividend_neg_o, -a, a))
  55
  56         # check for absolute overflow condition (32/64)
  57         comb += self.o.dive_abs_ov64.eq((abs_dend >= abs_dor)
  58                                         & (op.insn_type == InternalOp.OP_DIVE))
  59
  60         comb += self.o.dive_abs_ov32.eq((abs_dend[0:32] >= abs_dor[0:32])
  61                                         & (op.insn_type == InternalOp.OP_DIVE))
  62
  63         # set divisor based on 32/64 bit mode (must be absolute)
  64         comb += eq32(op.is_32bit, divisor_o, abs_dor)
  65
  66         # divide by zero error detection
  67         comb += self.o.div_by_zero.eq(divisor_o == 0)
  68
  69         ##########################
  70         # main switch for DIV
  71
  72         with m.Switch(op.insn_type):
  73             # div/mod takes straight (absolute) dividend
  74             with m.Case(InternalOp.OP_DIV, InternalOp.OP_MOD):
  75                 comb += eq32(op.is_32bit, dividend_o, abs_dend)
  76             # extended div shifts dividend up
  77             with m.Case(InternalOp.OP_DIVE):
  78                 with m.If(op.is_32bit):
  79                     comb += dividend_o.eq(abs_dend[0:32] << 32)
  80                 with m.Else():
  81                     comb += dividend_o.eq(abs_dend[0:64] << 64)
  82
  83         ###### sticky overflow and context, both pass-through #####
  84
  85         comb += self.o.xer_so.eq(self.i.xer_so)
  86         comb += self.o.ctx.eq(self.i.ctx)
  87
  88         return m