1 # This stage is the setup stage that converts the inputs
2 # into the values expected by DivPipeCore
4 from nmigen
import (Module
, Signal
, Cat
, Repl
, Mux
, Const
, Array
)
5 from nmutil
.pipemodbase
import PipeModBase
6 from soc
.fu
.div
.pipe_data
import DivInputData
7 from ieee754
.part
.partsig
import PartitionedSignal
8 from soc
.decoder
.power_enums
import MicrOp
10 from soc
.decoder
.power_fields
import DecodeFields
11 from soc
.decoder
.power_fieldsn
import SignalBitRange
12 from soc
.fu
.div
.pipe_data
import CoreInputData
13 from ieee754
.div_rem_sqrt_rsqrt
.core
import DivPipeCoreOperation
14 from nmutil
.util
import eq32
17 class DivSetupStage(PipeModBase
):
18 def __init__(self
, pspec
):
19 super().__init
__(pspec
, "setup_stage")
20 self
.fields
= DecodeFields(SignalBitRange
, [self
.i
.ctx
.op
.insn
])
21 self
.fields
.create_specs()
24 return DivInputData(self
.pspec
)
27 return CoreInputData(self
.pspec
)
29 def elaborate(self
, platform
):
32 # convenience variables
33 op
, a
, b
= self
.i
.ctx
.op
, self
.i
.a
, self
.i
.b
35 dividend_neg_o
= self
.o
.dividend_neg
36 divisor_neg_o
= self
.o
.divisor_neg
37 dividend_o
= core_o
.dividend
38 divisor_o
= core_o
.divisor_radicand
40 # set operation to unsigned div/remainder
41 comb
+= core_o
.operation
.eq(int(DivPipeCoreOperation
.UDivRem
))
43 # work out if a/b are negative (check 32-bit / signed)
44 comb
+= dividend_neg_o
.eq(Mux(op
.is_32bit
,
45 a
[31], a
[63]) & op
.is_signed
)
46 comb
+= divisor_neg_o
.eq(Mux(op
.is_32bit
, b
[31], b
[63]) & op
.is_signed
)
48 # negation of a 64-bit value produces the same lower 32-bit
49 # result as negation of just the lower 32-bits, so we don't
50 # need to do anything special before negating
51 abs_dor
= Signal(64, reset_less
=True) # absolute of divisor
52 abs_dend
= Signal(64, reset_less
=True) # absolute of dividend
53 comb
+= abs_dor
.eq(Mux(divisor_neg_o
, -b
, b
))
54 comb
+= abs_dend
.eq(Mux(dividend_neg_o
, -a
, a
))
56 # check for absolute overflow condition (32/64)
57 comb
+= self
.o
.dive_abs_ov64
.eq((abs_dend
>= abs_dor
)
58 & (op
.insn_type
== MicrOp
.OP_DIVE
))
60 comb
+= self
.o
.dive_abs_ov32
.eq((abs_dend
[0:32] >= abs_dor
[0:32])
61 & (op
.insn_type
== MicrOp
.OP_DIVE
))
63 # set divisor based on 32/64 bit mode (must be absolute)
64 comb
+= eq32(op
.is_32bit
, divisor_o
, abs_dor
)
66 # divide by zero error detection
67 comb
+= self
.o
.div_by_zero
.eq(divisor_o
== 0)
69 ##########################
72 with m
.Switch(op
.insn_type
):
73 # div/mod takes straight (absolute) dividend
74 with m
.Case(MicrOp
.OP_DIV
, MicrOp
.OP_MOD
):
75 comb
+= eq32(op
.is_32bit
, dividend_o
, abs_dend
)
76 # extended div shifts dividend up
77 with m
.Case(MicrOp
.OP_DIVE
):
78 with m
.If(op
.is_32bit
):
79 comb
+= dividend_o
.eq(abs_dend
[0:32] << 32)
81 comb
+= dividend_o
.eq(abs_dend
[0:64] << 64)
83 ###### sticky overflow and context, both pass-through #####
85 comb
+= self
.o
.xer_so
.eq(self
.i
.xer_so
)
86 comb
+= self
.o
.ctx
.eq(self
.i
.ctx
)