3 based on microwatt loadstore1.vhdl, but conforming to PortInterface.
4 unlike loadstore1.vhdl this does *not* deal with actual Load/Store
5 ops: that job is handled by LDSTCompUnit, which talks to LoadStore1
6 by way of PortInterface. PortInterface is where things need extending,
7 such as adding dcbz support, etc.
9 this module basically handles "pure" load / store operations, and
10 its first job is to ask the D-Cache for the data. if that fails,
11 the second task (if virtual memory is enabled) is to ask the MMU
12 to perform a TLB, then to go *back* to the cache and ask again.
16 * https://bugs.libre-soc.org/show_bug.cgi?id=465
20 from nmigen
import (Elaboratable
, Module
, Signal
, Shape
, unsigned
, Cat
, Mux
,
23 from nmutil
.util
import rising_edge
24 from enum
import Enum
, unique
26 from soc
.experiment
.dcache
import DCache
27 from soc
.experiment
.pimem
import PortInterfaceBase
28 from soc
.experiment
.mem_types
import LoadStore1ToMMUType
29 from soc
.experiment
.mem_types
import MMUToLoadStore1Type
31 from soc
.minerva
.wishbone
import make_wb_layout
32 from soc
.bus
.sram
import SRAM
33 from nmutil
.util
import Display
38 IDLE
= 0 # ready for instruction
39 ACK_WAIT
= 1 # waiting for ack from dcache
40 MMU_LOOKUP
= 2 # waiting for MMU to look up translation
41 TLBIE_WAIT
= 3 # waiting for MMU to finish doing a tlbie
44 # glue logic for microwatt mmu and dcache
45 class LoadStore1(PortInterfaceBase
):
46 def __init__(self
, pspec
):
48 self
.disable_cache
= (hasattr(pspec
, "disable_cache") and
49 pspec
.disable_cache
== True)
50 regwid
= pspec
.reg_wid
51 addrwid
= pspec
.addr_wid
53 super().__init
__(regwid
, addrwid
)
54 self
.dcache
= DCache()
55 # these names are from the perspective of here (LoadStore1)
56 self
.d_out
= self
.dcache
.d_in
# in to dcache is out for LoadStore
57 self
.d_in
= self
.dcache
.d_out
# out from dcache is in for LoadStore
58 self
.m_out
= LoadStore1ToMMUType() # out *to* MMU
59 self
.m_in
= MMUToLoadStore1Type() # in *from* MMU
61 # TODO, convert dcache wb_in/wb_out to "standard" nmigen Wishbone bus
62 self
.dbus
= Record(make_wb_layout(pspec
))
64 # for creating a single clock blip to DCache
65 self
.d_valid
= Signal()
66 self
.d_w_valid
= Signal()
67 self
.d_validblip
= Signal()
69 # DSISR and DAR cached values. note that the MMU FSM is where
70 # these are accessed by OP_MTSPR/OP_MFSPR, on behalf of LoadStore1.
71 # by contrast microwatt has the spr set/get done *in* loadstore1.vhdl
72 self
.dsisr
= Signal(64)
75 # state info for LD/ST
77 # latch most of the input request
81 self
.addr
= Signal(64)
82 self
.store_data
= Signal(64)
83 self
.load_data
= Signal(64)
84 self
.byte_sel
= Signal(8)
85 self
.update
= Signal()
86 #self.xerc : xer_common_t;
87 #self.reserve = Signal()
88 #self.atomic = Signal()
89 #self.atomic_last = Signal()
91 self
.nc
= Signal() # non-cacheable access
92 self
.virt_mode
= Signal()
93 self
.priv_mode
= Signal()
94 self
.state
= Signal(State
)
95 self
.instr_fault
= Signal()
96 self
.align_intr
= Signal()
98 self
.wait_dcache
= Signal()
99 self
.wait_mmu
= Signal()
100 #self.mode_32bit = Signal()
101 self
.wr_sel
= Signal(2)
102 self
.interrupt
= Signal()
103 #self.intr_vec : integer range 0 to 16#fff#;
104 #self.nia = Signal(64)
105 #self.srr1 = Signal(16)
107 def set_wr_addr(self
, m
, addr
, mask
, misalign
, msr_pr
):
108 m
.d
.comb
+= self
.load
.eq(0) # store operation
110 m
.d
.comb
+= self
.d_out
.load
.eq(0)
111 m
.d
.comb
+= self
.byte_sel
.eq(mask
)
112 m
.d
.comb
+= self
.addr
.eq(addr
)
113 m
.d
.comb
+= self
.priv_mode
.eq(~msr_pr
) # not-problem ==> priv
114 m
.d
.comb
+= self
.virt_mode
.eq(msr_pr
) # problem-state ==> virt
115 m
.d
.comb
+= self
.align_intr
.eq(misalign
)
116 # option to disable the cache entirely for write
117 if self
.disable_cache
:
118 m
.d
.comb
+= self
.nc
.eq(1)
121 def set_rd_addr(self
, m
, addr
, mask
, misalign
, msr_pr
):
122 m
.d
.comb
+= self
.d_valid
.eq(1)
123 m
.d
.comb
+= self
.d_out
.valid
.eq(self
.d_validblip
)
124 m
.d
.comb
+= self
.load
.eq(1) # load operation
125 m
.d
.comb
+= self
.d_out
.load
.eq(1)
126 m
.d
.comb
+= self
.byte_sel
.eq(mask
)
127 m
.d
.comb
+= self
.align_intr
.eq(misalign
)
128 m
.d
.comb
+= self
.addr
.eq(addr
)
129 m
.d
.comb
+= self
.priv_mode
.eq(~msr_pr
) # not-problem ==> priv
130 m
.d
.comb
+= self
.virt_mode
.eq(msr_pr
) # problem-state ==> virt
131 # BAD HACK! disable cacheing on LD when address is 0xCxxx_xxxx
132 # this is for peripherals. same thing done in Microwatt loadstore1.vhdl
133 with m
.If(addr
[28:] == Const(0xc, 4)):
134 m
.d
.comb
+= self
.nc
.eq(1)
135 # option to disable the cache entirely for read
136 if self
.disable_cache
:
137 m
.d
.comb
+= self
.nc
.eq(1)
138 return None #FIXME return value
140 def set_wr_data(self
, m
, data
, wen
):
141 # do the "blip" on write data
142 m
.d
.comb
+= self
.d_valid
.eq(1)
143 m
.d
.comb
+= self
.d_out
.valid
.eq(self
.d_validblip
)
144 # put data into comb which is picked up in main elaborate()
145 m
.d
.comb
+= self
.d_w_valid
.eq(1)
146 m
.d
.comb
+= self
.store_data
.eq(data
)
147 #m.d.sync += self.d_out.byte_sel.eq(wen) # this might not be needed
148 st_ok
= self
.done
# TODO indicates write data is valid
151 def get_rd_data(self
, m
):
152 ld_ok
= self
.done
# indicates read data is valid
153 data
= self
.load_data
# actual read data
156 def elaborate(self
, platform
):
157 m
= super().elaborate(platform
)
158 comb
, sync
= m
.d
.comb
, m
.d
.sync
160 # create dcache module
161 m
.submodules
.dcache
= dcache
= self
.dcache
164 d_out
, d_in
, dbus
= self
.d_out
, self
.d_in
, self
.dbus
165 m_out
, m_in
= self
.m_out
, self
.m_in
167 exception
= exc
.happened
170 # copy of address, but gets over-ridden for OP_FETCH_FAILED
172 m
.d
.comb
+= maddr
.eq(self
.addr
)
174 # create a blip (single pulse) on valid read/write request
175 # this can be over-ridden in the FSM to get dcache to re-run
176 # a request when MMU_LOOKUP completes
177 m
.d
.comb
+= self
.d_validblip
.eq(rising_edge(m
, self
.d_valid
))
180 with m
.Switch(self
.state
):
181 with m
.Case(State
.IDLE
):
182 with m
.If(self
.d_validblip
):
183 sync
+= self
.state
.eq(State
.ACK_WAIT
)
185 # waiting for completion
186 with m
.Case(State
.ACK_WAIT
):
188 with m
.If(d_in
.error
):
189 # cache error is not necessarily "final", it could
190 # be that it was just a TLB miss
191 with m
.If(d_in
.cache_paradox
):
192 comb
+= exception
.eq(1)
193 sync
+= self
.state
.eq(State
.IDLE
)
194 sync
+= self
.dsisr
[63 - 38].eq(~self
.load
)
195 # XXX there is no architected bit for this
196 # (probably should be a machine check in fact)
197 sync
+= self
.dsisr
[63 - 35].eq(d_in
.cache_paradox
)
200 # Look up the translation for TLB miss
201 # and also for permission error and RC error
202 # in case the PTE has been updated.
204 sync
+= self
.state
.eq(State
.MMU_LOOKUP
)
205 with m
.If(d_in
.valid
):
206 m
.d
.comb
+= self
.done
.eq(1)
207 sync
+= self
.state
.eq(State
.IDLE
)
208 with m
.If(self
.load
):
209 m
.d
.comb
+= self
.load_data
.eq(d_in
.data
)
211 # waiting here for the MMU TLB lookup to complete.
212 # either re-try the dcache lookup or throw MMU exception
213 with m
.Case(State
.MMU_LOOKUP
):
214 with m
.If(m_in
.done
):
215 with m
.If(~self
.instr_fault
):
216 sync
+= Display("MMU_LOOKUP, done %x", self
.addr
)
217 # retry the request now that the MMU has
218 # installed a TLB entry
219 m
.d
.comb
+= self
.d_validblip
.eq(1) # re-run dcache req
220 sync
+= self
.state
.eq(State
.ACK_WAIT
)
222 sync
+= Display("MMU_LOOKUP, exception %x", self
.addr
)
223 # instruction lookup fault: store address in DAR
224 comb
+= exc
.happened
.eq(1)
225 sync
+= self
.dar
.eq(self
.addr
)
228 # MMU RADIX exception thrown
229 comb
+= exception
.eq(1)
230 sync
+= self
.dsisr
[63 - 33].eq(m_in
.invalid
)
231 sync
+= self
.dsisr
[63 - 36].eq(m_in
.perm_error
)
232 sync
+= self
.dsisr
[63 - 38].eq(self
.load
)
233 sync
+= self
.dsisr
[63 - 44].eq(m_in
.badtree
)
234 sync
+= self
.dsisr
[63 - 45].eq(m_in
.rc_error
)
236 with m
.Case(State
.TLBIE_WAIT
):
239 # alignment error: store address in DAR
240 with m
.If(self
.align_intr
):
241 comb
+= exc
.happened
.eq(1)
242 sync
+= self
.dar
.eq(self
.addr
)
244 # happened, alignment, instr_fault, invalid.
245 # note that all of these flow through - eventually to the TRAP
246 # pipeline, via PowerDecoder2.
247 comb
+= exc
.invalid
.eq(m_in
.invalid
)
248 comb
+= exc
.alignment
.eq(self
.align_intr
)
249 comb
+= exc
.instr_fault
.eq(self
.instr_fault
)
250 # badtree, perm_error, rc_error, segment_fault
251 comb
+= exc
.badtree
.eq(m_in
.badtree
)
252 comb
+= exc
.perm_error
.eq(m_in
.perm_error
)
253 comb
+= exc
.rc_error
.eq(m_in
.rc_error
)
254 comb
+= exc
.segment_fault
.eq(m_in
.segerr
)
256 # TODO, connect dcache wb_in/wb_out to "standard" nmigen Wishbone bus
257 comb
+= dbus
.adr
.eq(dcache
.wb_out
.adr
)
258 comb
+= dbus
.dat_w
.eq(dcache
.wb_out
.dat
)
259 comb
+= dbus
.sel
.eq(dcache
.wb_out
.sel
)
260 comb
+= dbus
.cyc
.eq(dcache
.wb_out
.cyc
)
261 comb
+= dbus
.stb
.eq(dcache
.wb_out
.stb
)
262 comb
+= dbus
.we
.eq(dcache
.wb_out
.we
)
264 comb
+= dcache
.wb_in
.dat
.eq(dbus
.dat_r
)
265 comb
+= dcache
.wb_in
.ack
.eq(dbus
.ack
)
266 if hasattr(dbus
, "stall"):
267 comb
+= dcache
.wb_in
.stall
.eq(dbus
.stall
)
269 # write out d data only when flag set
270 with m
.If(self
.d_w_valid
):
271 m
.d
.sync
+= d_out
.data
.eq(self
.store_data
)
273 m
.d
.sync
+= d_out
.data
.eq(0)
275 # this must move into the FSM, conditionally noticing that
276 # the "blip" comes from self.d_validblip.
277 # task 1: look up in dcache
278 # task 2: if dcache fails, look up in MMU.
279 # do **NOT** confuse the two.
280 m
.d
.comb
+= d_out
.load
.eq(self
.load
)
281 m
.d
.comb
+= d_out
.byte_sel
.eq(self
.byte_sel
)
282 m
.d
.comb
+= d_out
.addr
.eq(self
.addr
)
283 m
.d
.comb
+= d_out
.nc
.eq(self
.nc
)
284 m
.d
.comb
+= d_out
.priv_mode
.eq(self
.priv_mode
)
285 m
.d
.comb
+= d_out
.virt_mode
.eq(self
.virt_mode
)
287 # XXX these should be possible to remove but for some reason
288 # cannot be... yet. TODO, investigate
289 m
.d
.comb
+= self
.done
.eq(d_in
.valid
)
290 m
.d
.comb
+= self
.load_data
.eq(d_in
.data
)
292 # Update outputs to MMU
293 m
.d
.comb
+= m_out
.valid
.eq(mmureq
)
294 m
.d
.comb
+= m_out
.iside
.eq(self
.instr_fault
)
295 m
.d
.comb
+= m_out
.load
.eq(self
.load
)
296 # m_out.priv <= r.priv_mode; TODO
297 m
.d
.comb
+= m_out
.tlbie
.eq(self
.tlbie
)
298 # m_out.mtspr <= mmu_mtspr; # TODO
299 # m_out.sprn <= sprn; # TODO
300 m
.d
.comb
+= m_out
.addr
.eq(maddr
)
301 # m_out.slbia <= l_in.insn(7); # TODO: no idea what this is
302 # m_out.rs <= l_in.data; # nope, probably not needed, TODO investigate
307 yield from super().ports()
311 class TestSRAMLoadStore1(LoadStore1
):
312 def __init__(self
, pspec
):
313 super().__init
__(pspec
)
315 # small 32-entry Memory
316 if (hasattr(pspec
, "dmem_test_depth") and
317 isinstance(pspec
.dmem_test_depth
, int)):
318 depth
= pspec
.dmem_test_depth
321 print("TestSRAMBareLoadStoreUnit depth", depth
)
323 self
.mem
= Memory(width
=pspec
.reg_wid
, depth
=depth
)
325 def elaborate(self
, platform
):
326 m
= super().elaborate(platform
)
328 m
.submodules
.sram
= sram
= SRAM(memory
=self
.mem
, granularity
=8,
329 features
={'cti', 'bte', 'err'})
332 # directly connect the wishbone bus of LoadStoreUnitInterface to SRAM
333 # note: SRAM is a target (slave), dbus is initiator (master)
334 fanouts
= ['dat_w', 'sel', 'cyc', 'stb', 'we', 'cti', 'bte']
335 fanins
= ['dat_r', 'ack', 'err']
336 for fanout
in fanouts
:
337 print("fanout", fanout
, getattr(sram
.bus
, fanout
).shape(),
338 getattr(dbus
, fanout
).shape())
339 comb
+= getattr(sram
.bus
, fanout
).eq(getattr(dbus
, fanout
))
340 comb
+= getattr(sram
.bus
, fanout
).eq(getattr(dbus
, fanout
))
342 comb
+= getattr(dbus
, fanin
).eq(getattr(sram
.bus
, fanin
))
344 comb
+= sram
.bus
.adr
.eq(dbus
.adr
)