1 from nmigen
import (Elaboratable
, Module
, Signal
, Shape
, unsigned
, Cat
, Mux
,
4 from nmutil
.util
import rising_edge
5 from enum
import Enum
, unique
7 from soc
.experiment
.dcache
import DCache
8 from soc
.experiment
.pimem
import PortInterfaceBase
9 from soc
.experiment
.mem_types
import LoadStore1ToMMUType
10 from soc
.experiment
.mem_types
import MMUToLoadStore1Type
12 from soc
.minerva
.wishbone
import make_wb_layout
13 from soc
.bus
.sram
import SRAM
18 IDLE
= 0 # ready for instruction
19 SECOND_REQ
= 1 # send 2nd request of unaligned xfer
20 ACK_WAIT
= 2 # waiting for ack from dcache
21 MMU_LOOKUP
= 3 # waiting for MMU to look up translation
22 TLBIE_WAIT
= 4 # waiting for MMU to finish doing a tlbie
23 FINISH_LFS
= 5 # write back converted SP data for lfs*
24 COMPLETE
= 6 # extra cycle to complete an operation
27 # glue logic for microwatt mmu and dcache
28 class LoadStore1(PortInterfaceBase
):
29 def __init__(self
, pspec
):
31 self
.disable_cache
= (hasattr(pspec
, "disable_cache") and
32 pspec
.disable_cache
== True)
33 regwid
= pspec
.reg_wid
34 addrwid
= pspec
.addr_wid
36 super().__init
__(regwid
, addrwid
)
37 self
.dcache
= DCache()
38 self
.d_in
= self
.dcache
.d_in
39 self
.d_out
= self
.dcache
.d_out
40 self
.l_in
= LoadStore1ToMMUType()
41 self
.l_out
= MMUToLoadStore1Type()
43 self
.mmureq
= Signal()
44 self
.derror
= Signal()
46 # TODO, convert dcache wb_in/wb_out to "standard" nmigen Wishbone bus
47 self
.dbus
= Record(make_wb_layout(pspec
))
49 # for creating a single clock blip to DCache
50 self
.d_valid
= Signal()
51 self
.d_w_valid
= Signal()
52 self
.d_validblip
= Signal()
54 # DSISR and DAR cached values. note that the MMU FSM is where
55 # these are accessed by OP_MTSPR/OP_MFSPR, on behalf of LoadStore1.
56 # by contrast microwatt has the spr set/get done *in* loadstore1.vhdl
57 self
.dsisr
= Signal(64)
60 # state info for LD/ST
62 # latch most of the input request
66 self
.addr
= Signal(64)
67 self
.store_data
= Signal(64)
68 self
.load_data
= Signal(64)
69 self
.byte_sel
= Signal(8)
70 self
.update
= Signal()
71 #self.xerc : xer_common_t;
72 #self.reserve = Signal()
73 #self.atomic = Signal()
74 #self.atomic_last = Signal()
76 self
.nc
= Signal() # non-cacheable access
77 self
.virt_mode
= Signal()
78 self
.priv_mode
= Signal()
79 self
.state
= Signal(State
)
80 self
.instr_fault
= Signal()
81 self
.align_intr
= Signal()
83 self
.wait_dcache
= Signal()
84 self
.wait_mmu
= Signal()
85 #self.mode_32bit = Signal()
86 self
.wr_sel
= Signal(2)
87 self
.interrupt
= Signal()
88 #self.intr_vec : integer range 0 to 16#fff#;
89 #self.nia = Signal(64)
90 #self.srr1 = Signal(16)
92 def set_wr_addr(self
, m
, addr
, mask
):
93 m
.d
.comb
+= self
.load
.eq(0) # store operation
95 m
.d
.comb
+= self
.d_in
.load
.eq(0)
96 m
.d
.comb
+= self
.byte_sel
.eq(mask
)
97 m
.d
.comb
+= self
.addr
.eq(addr
)
98 # option to disable the cache entirely for write
99 if self
.disable_cache
:
100 m
.d
.comb
+= self
.nc
.eq(1)
103 def set_rd_addr(self
, m
, addr
, mask
):
104 m
.d
.comb
+= self
.d_valid
.eq(1)
105 m
.d
.comb
+= self
.d_in
.valid
.eq(self
.d_validblip
)
106 m
.d
.comb
+= self
.load
.eq(1) # load operation
107 m
.d
.comb
+= self
.d_in
.load
.eq(1)
108 m
.d
.comb
+= self
.byte_sel
.eq(mask
)
109 m
.d
.comb
+= self
.addr
.eq(addr
)
110 # BAD HACK! disable cacheing on LD when address is 0xCxxx_xxxx
111 # this is for peripherals. same thing done in Microwatt loadstore1.vhdl
112 with m
.If(addr
[28:] == Const(0xc, 4)):
113 m
.d
.comb
+= self
.nc
.eq(1)
114 # option to disable the cache entirely for read
115 if self
.disable_cache
:
116 m
.d
.comb
+= self
.nc
.eq(1)
117 return None #FIXME return value
119 def set_wr_data(self
, m
, data
, wen
):
120 # do the "blip" on write data
121 m
.d
.comb
+= self
.d_valid
.eq(1)
122 m
.d
.comb
+= self
.d_in
.valid
.eq(self
.d_validblip
)
123 # put data into comb which is picked up in main elaborate()
124 m
.d
.comb
+= self
.d_w_valid
.eq(1)
125 m
.d
.comb
+= self
.store_data
.eq(data
)
126 #m.d.sync += self.d_in.byte_sel.eq(wen) # this might not be needed
127 st_ok
= self
.done
# TODO indicates write data is valid
131 def get_rd_data(self
, m
):
132 ld_ok
= self
.done
# indicates read data is valid
133 data
= self
.load_data
# actual read data
137 if d_in.error = '1' then
138 if d_in.cache_paradox = '1' then
139 -- signal an interrupt straight away
141 dsisr(63 - 38) := not r2.req.load;
142 -- XXX there is no architected bit for this
143 -- (probably should be a machine check in fact)
144 dsisr(63 - 35) := d_in.cache_paradox;
146 -- Look up the translation for TLB miss
147 -- and also for permission error and RC error
148 -- in case the PTE has been updated.
150 v.state := MMU_LOOKUP;
156 def elaborate(self
, platform
):
157 m
= super().elaborate(platform
)
158 comb
, sync
= m
.d
.comb
, m
.d
.sync
160 # create dcache module
161 m
.submodules
.dcache
= dcache
= self
.dcache
164 d_in
, d_out
, l_out
, dbus
= self
.d_in
, self
.d_out
, self
.l_out
, self
.dbus
166 with m
.If(d_out
.error
):
167 with m
.If(d_out
.cache_paradox
):
168 sync
+= self
.derror
.eq(1)
169 sync
+= self
.dsisr
[63 - 38].eq(~self
.load
)
170 # XXX there is no architected bit for this
171 # (probably should be a machine check in fact)
172 sync
+= self
.dsisr
[63 - 35].eq(d_out
.cache_paradox
)
175 # Look up the translation for TLB miss
176 # and also for permission error and RC error
177 # in case the PTE has been updated.
178 sync
+= self
.mmureq
.eq(1)
179 sync
+= self
.state
.eq(State
.MMU_LOOKUP
)
183 # happened, alignment, instr_fault, invalid,
184 comb
+= exc
.happened
.eq(d_out
.error | l_out
.err
)
185 comb
+= exc
.invalid
.eq(l_out
.invalid
)
187 # badtree, perm_error, rc_error, segment_fault
188 comb
+= exc
.badtree
.eq(l_out
.badtree
)
189 comb
+= exc
.perm_error
.eq(l_out
.perm_error
)
190 comb
+= exc
.rc_error
.eq(l_out
.rc_error
)
191 comb
+= exc
.segment_fault
.eq(l_out
.segerr
)
193 # TODO some exceptions set SPRs
195 # TODO, connect dcache wb_in/wb_out to "standard" nmigen Wishbone bus
196 comb
+= dbus
.adr
.eq(dcache
.wb_out
.adr
)
197 comb
+= dbus
.dat_w
.eq(dcache
.wb_out
.dat
)
198 comb
+= dbus
.sel
.eq(dcache
.wb_out
.sel
)
199 comb
+= dbus
.cyc
.eq(dcache
.wb_out
.cyc
)
200 comb
+= dbus
.stb
.eq(dcache
.wb_out
.stb
)
201 comb
+= dbus
.we
.eq(dcache
.wb_out
.we
)
203 comb
+= dcache
.wb_in
.dat
.eq(dbus
.dat_r
)
204 comb
+= dcache
.wb_in
.ack
.eq(dbus
.ack
)
205 if hasattr(dbus
, "stall"):
206 comb
+= dcache
.wb_in
.stall
.eq(dbus
.stall
)
208 # create a blip (single pulse) on valid read/write request
209 m
.d
.comb
+= self
.d_validblip
.eq(rising_edge(m
, self
.d_valid
))
211 # write out d data only when flag set
212 with m
.If(self
.d_w_valid
):
213 m
.d
.sync
+= self
.d_in
.data
.eq(self
.store_data
)
215 m
.d
.sync
+= self
.d_in
.data
.eq(0)
217 m
.d
.comb
+= self
.d_in
.load
.eq(self
.load
)
218 m
.d
.comb
+= self
.d_in
.byte_sel
.eq(self
.byte_sel
)
219 m
.d
.comb
+= self
.d_in
.addr
.eq(self
.addr
)
220 m
.d
.comb
+= self
.d_in
.nc
.eq(self
.nc
)
221 m
.d
.comb
+= self
.done
.eq(self
.d_out
.valid
)
222 m
.d
.comb
+= self
.load_data
.eq(d_out
.data
)
227 yield from super().ports()
231 class TestSRAMLoadStore1(LoadStore1
):
232 def __init__(self
, pspec
):
233 super().__init
__(pspec
)
235 # small 32-entry Memory
236 if (hasattr(pspec
, "dmem_test_depth") and
237 isinstance(pspec
.dmem_test_depth
, int)):
238 depth
= pspec
.dmem_test_depth
241 print("TestSRAMBareLoadStoreUnit depth", depth
)
243 self
.mem
= Memory(width
=pspec
.reg_wid
, depth
=depth
)
245 def elaborate(self
, platform
):
246 m
= super().elaborate(platform
)
248 m
.submodules
.sram
= sram
= SRAM(memory
=self
.mem
, granularity
=8,
249 features
={'cti', 'bte', 'err'})
252 # directly connect the wishbone bus of LoadStoreUnitInterface to SRAM
253 # note: SRAM is a target (slave), dbus is initiator (master)
254 fanouts
= ['dat_w', 'sel', 'cyc', 'stb', 'we', 'cti', 'bte']
255 fanins
= ['dat_r', 'ack', 'err']
256 for fanout
in fanouts
:
257 print("fanout", fanout
, getattr(sram
.bus
, fanout
).shape(),
258 getattr(dbus
, fanout
).shape())
259 comb
+= getattr(sram
.bus
, fanout
).eq(getattr(dbus
, fanout
))
260 comb
+= getattr(sram
.bus
, fanout
).eq(getattr(dbus
, fanout
))
262 comb
+= getattr(dbus
, fanin
).eq(getattr(sram
.bus
, fanin
))
264 comb
+= sram
.bus
.adr
.eq(dbus
.adr
)