src/soc/fu/logical/main_stage.py

   1 # This stage is intended to do most of the work of executing Logical
   2 # instructions. This is OR, AND, XOR, POPCNT, PRTY, CMPB, BPERMD, CNTLZ
   3 # however input and output stages also perform bit-negation on input(s)
   4 # and output, as well as carry and overflow generation.
   5 # This module however should not gate the carry or overflow, that's up
   6 # to the output stage
   7
   8 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
   9 from nmutil.pipemodbase import PipeModBase
  10 from nmutil.clz import CLZ
  11 from soc.fu.logical.pipe_data import LogicalInputData
  12 from soc.fu.logical.bpermd import Bpermd
  13 from soc.fu.logical.pipe_data import LogicalOutputData
  14 from ieee754.part.partsig import PartitionedSignal
  15 from soc.decoder.power_enums import InternalOp
  16
  17 from soc.decoder.power_fields import DecodeFields
  18 from soc.decoder.power_fieldsn import SignalBitRange
  19
  20
  21 def array_of(count, bitwidth):
  22     res = []
  23     for i in range(count):
  24         res.append(Signal(bitwidth, reset_less=True,
  25                           name=f"pop_{bitwidth}_{i}"))
  26     return res
  27
  28
  29 class LogicalMainStage(PipeModBase):
  30     def __init__(self, pspec):
  31         super().__init__(pspec, "main")
  32         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
  33         self.fields.create_specs()
  34
  35     def ispec(self):
  36         return LogicalInputData(self.pspec)
  37
  38     def ospec(self):
  39         return LogicalOutputData(self.pspec)
  40
  41     def elaborate(self, platform):
  42         m = Module()
  43         comb = m.d.comb
  44         op, a, b, o = self.i.ctx.op, self.i.a, self.i.b, self.o.o
  45
  46         comb += o.ok.eq(1) # overridden if no op activates
  47
  48         m.submodules.bpermd = bpermd = Bpermd(64)
  49
  50         ##########################
  51         # main switch for logic ops AND, OR and XOR, cmpb, parity, and popcount
  52
  53         with m.Switch(op.insn_type):
  54
  55             ###### AND, OR, XOR #######
  56             with m.Case(InternalOp.OP_AND):
  57                 comb += o.data.eq(a & b)
  58             with m.Case(InternalOp.OP_OR):
  59                 comb += o.data.eq(a | b)
  60             with m.Case(InternalOp.OP_XOR):
  61                 comb += o.data.eq(a ^ b)
  62
  63             ###### cmpb #######
  64             with m.Case(InternalOp.OP_CMPB):
  65                 l = []
  66                 for i in range(8):
  67                     slc = slice(i*8, (i+1)*8)
  68                     l.append(Repl(a[slc] == b[slc], 8))
  69                 comb += o.data.eq(Cat(*l))
  70
  71             ###### popcount #######
  72             with m.Case(InternalOp.OP_POPCNT):
  73                 # starting from a, perform successive addition-reductions
  74                 # creating arrays big enough to store the sum, each time
  75                 pc = [a]
  76                 # QTY32 2-bit (to take 2x 1-bit sums) etc.
  77                 work = [(32, 2), (16, 3), (8, 4), (4, 5), (2, 6), (1, 7)]
  78                 for l, bw in work:
  79                     pc.append(array_of(l, bw))
  80                 pc8 = pc[3]     # array of 8 8-bit counts (popcntb)
  81                 pc32 = pc[5]    # array of 2 32-bit counts (popcntw)
  82                 popcnt = pc[-1]  # array of 1 64-bit count (popcntd)
  83                 # cascade-tree of adds
  84                 for idx, (l, bw) in enumerate(work):
  85                     for i in range(l):
  86                         stt, end = i*2, i*2+1
  87                         src, dst = pc[idx], pc[idx+1]
  88                         comb += dst[i].eq(Cat(src[stt], Const(0, 1)) +
  89                                           Cat(src[end], Const(0, 1)))
  90                 # decode operation length
  91                 with m.If(op.data_len == 1):
  92                     # popcntb - pack 8x 4-bit answers into output
  93                     for i in range(8):
  94                         comb += o[i*8:(i+1)*8].eq(pc8[i])
  95                 with m.Elif(op.data_len == 4):
  96                     # popcntw - pack 2x 5-bit answers into output
  97                     for i in range(2):
  98                         comb += o[i*32:(i+1)*32].eq(pc32[i])
  99                 with m.Else():
 100                     # popcntd - put 1x 6-bit answer into output
 101                     comb += o.data.eq(popcnt[0])
 102
 103             ###### parity #######
 104             with m.Case(InternalOp.OP_PRTY):
 105                 # strange instruction which XORs together the LSBs of each byte
 106                 par0 = Signal(reset_less=True)
 107                 par1 = Signal(reset_less=True)
 108                 comb += par0.eq(Cat(a[0], a[8], a[16], a[24]).xor())
 109                 comb += par1.eq(Cat(a[32], a[40], a[48], a[56]).xor())
 110                 with m.If(op.data_len[3] == 1):
 111                     comb += o.data.eq(par0 ^ par1)
 112                 with m.Else():
 113                     comb += o[0].eq(par0)
 114                     comb += o[32].eq(par1)
 115
 116             ###### cntlz #######
 117             with m.Case(InternalOp.OP_CNTZ):
 118                 XO = self.fields.FormX.XO[0:-1]
 119                 count_right = Signal(reset_less=True)
 120                 comb += count_right.eq(XO[-1])
 121
 122                 cntz_i = Signal(64, reset_less=True)
 123                 a32 = Signal(32, reset_less=True)
 124                 comb += a32.eq(a[0:32])
 125
 126                 with m.If(op.is_32bit):
 127                     comb += cntz_i.eq(Mux(count_right, a32[::-1], a32))
 128                 with m.Else():
 129                     comb += cntz_i.eq(Mux(count_right, a[::-1], a))
 130
 131                 m.submodules.clz = clz = CLZ(64)
 132                 comb += clz.sig_in.eq(cntz_i)
 133                 comb += o.data.eq(Mux(op.is_32bit, clz.lz-32, clz.lz))
 134
 135             ###### bpermd #######
 136             with m.Case(InternalOp.OP_BPERM):
 137                 comb += bpermd.rs.eq(a)
 138                 comb += bpermd.rb.eq(b)
 139                 comb += o.data.eq(bpermd.ra)
 140
 141             with m.Default():
 142                 comb += o.ok.eq(0)
 143
 144         ###### context, pass-through #####
 145
 146         comb += self.o.ctx.eq(self.i.ctx)
 147
 148         return m