src/soc/fu/logical/pipe_data.py

   1 from nmigen import Signal, Const, Cat
   2 from ieee754.fpcommon.getop import FPPipeContext
   3 from soc.fu.pipe_data import IntegerData
   4 from soc.decoder.power_decoder2 import Data
   5 from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec
   6 from soc.fu.logical.logical_input_record import CompLogicalOpSubset
   7
   8
   9 class LogicalInputData(IntegerData):
  10     regspec = [('INT', 'ra', '0:63'), # RA
  11                ('INT', 'rb', '0:63'), # RB/immediate
  12                ]
  13     def __init__(self, pspec):
  14         super().__init__(pspec, False)
  15         # convenience
  16         self.a, self.b = self.ra, self.rb
  17
  18
  19 class LogicalOutputData(IntegerData):
  20     regspec = [('INT', 'o', '0:63'),        # RT
  21                ('CR', 'cr_a', '0:3'),
  22                ('XER', 'xer_ca', '34,45'), # bit0: ca, bit1: ca32
  23                ]
  24     def __init__(self, pspec):
  25         super().__init__(pspec, True)
  26         # convenience
  27         self.cr0 = self.cr_a
  28
  29
  30 class LogicalPipeSpec(CommonPipeSpec):
  31     regspec = (LogicalInputData.regspec, LogicalOutputData.regspec)
  32     opsubsetkls = CompLogicalOpSubset