src/soc/fu/logical/pipe_data.py

   1 from soc.fu.pipe_data import IntegerData
   2 from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec
   3 from soc.fu.logical.logical_input_record import CompLogicalOpSubset
   4
   5
   6 class LogicalInputData(IntegerData):
   7     regspec = [('INT', 'ra', '0:63'), # RA
   8                ('INT', 'rb', '0:63'), # RB/immediate
   9                ]
  10     def __init__(self, pspec):
  11         super().__init__(pspec, False)
  12         # convenience
  13         self.a, self.b = self.ra, self.rb
  14
  15
  16 class LogicalOutputData(IntegerData):
  17     regspec = [('INT', 'o', '0:63'),        # RT
  18                ('CR', 'cr_a', '0:3'),
  19                ('XER', 'xer_ca', '34,45'), # bit0: ca, bit1: ca32
  20                ]
  21     def __init__(self, pspec):
  22         super().__init__(pspec, True)
  23         # convenience
  24         self.cr0 = self.cr_a
  25
  26
  27 class LogicalPipeSpec(CommonPipeSpec):
  28     regspec = (LogicalInputData.regspec, LogicalOutputData.regspec)
  29     opsubsetkls = CompLogicalOpSubset