src/soc/fu/logical/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14 from soc.fu.test.common import TestCase
  15 from soc.fu.logical.pipeline import LogicalBasePipe
  16 from soc.fu.logical.pipe_data import LogicalPipeSpec
  17 import random
  18
  19
  20 def get_cu_inputs(dec2, sim):
  21     """naming (res) must conform to LogicalFunctionUnit input regspec
  22     """
  23     res = {}
  24
  25     # RA (or RC)
  26     reg1_ok = yield dec2.e.read_reg1.ok
  27     if reg1_ok:
  28         data1 = yield dec2.e.read_reg1.data
  29         res['ra'] = sim.gpr(data1).value
  30
  31     # RB (or immediate)
  32     reg2_ok = yield dec2.e.read_reg2.ok
  33     #imm_ok = yield dec2.e.imm_data.imm_ok
  34     if reg2_ok:
  35         data2 = yield dec2.e.read_reg2.data
  36         data2 = sim.gpr(data2).value
  37         res['rb'] = data2
  38     #elif imm_ok:
  39     #    data2 = yield dec2.e.imm_data.imm
  40     #    res['rb'] = data2
  41
  42     return res
  43
  44
  45 def set_alu_inputs(alu, dec2, sim):
  46     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  47     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  48     # and place it into data_i.b
  49
  50     inp = yield from get_cu_inputs(dec2, sim)
  51     if 'ra' in inp:
  52         yield alu.p.data_i.a.eq(inp['ra'])
  53     if 'rb' in inp:
  54         yield alu.p.data_i.b.eq(inp['rb'])
  55     imm_ok = yield dec2.e.imm_data.imm_ok
  56     if imm_ok:
  57         data2 = yield dec2.e.imm_data.imm
  58         yield alu.p.data_i.b.eq(data2)
  59
  60
  61 # This test bench is a bit different than is usual. Initially when I
  62 # was writing it, I had all of the tests call a function to create a
  63 # device under test and simulator, initialize the dut, run the
  64 # simulation for ~2 cycles, and assert that the dut output what it
  65 # should have. However, this was really slow, since it needed to
  66 # create and tear down the dut and simulator for every test case.
  67
  68 # Now, instead of doing that, every test case in ALUTestCase puts some
  69 # data into the test_data list below, describing the instructions to
  70 # be tested and the initial state. Once all the tests have been run,
  71 # test_data gets passed to TestRunner which then sets up the DUT and
  72 # simulator once, runs all the data through it, and asserts that the
  73 # results match the pseudocode sim at every cycle.
  74
  75 # By doing this, I've reduced the time it takes to run the test suite
  76 # massively. Before, it took around 1 minute on my computer, now it
  77 # takes around 3 seconds
  78
  79
  80 class LogicalTestCase(FHDLTestCase):
  81     test_data = []
  82     def __init__(self, name):
  83         super().__init__(name)
  84         self.test_name = name
  85
  86     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
  87         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
  88         self.test_data.append(tc)
  89
  90     def test_rand(self):
  91         insns = ["and", "or", "xor"]
  92         for i in range(40):
  93             choice = random.choice(insns)
  94             lst = [f"{choice} 3, 1, 2"]
  95             initial_regs = [0] * 32
  96             initial_regs[1] = random.randint(0, (1 << 64)-1)
  97             initial_regs[2] = random.randint(0, (1 << 64)-1)
  98             self.run_tst_program(Program(lst), initial_regs)
  99
 100     def test_rand_imm_logical(self):
 101         insns = ["andi.", "andis.", "ori", "oris", "xori", "xoris"]
 102         for i in range(10):
 103             choice = random.choice(insns)
 104             imm = random.randint(0, (1 << 16)-1)
 105             lst = [f"{choice} 3, 1, {imm}"]
 106             print(lst)
 107             initial_regs = [0] * 32
 108             initial_regs[1] = random.randint(0, (1 << 64)-1)
 109             self.run_tst_program(Program(lst), initial_regs)
 110
 111     def test_cntz(self):
 112         insns = ["cntlzd", "cnttzd", "cntlzw", "cnttzw"]
 113         for i in range(100):
 114             choice = random.choice(insns)
 115             lst = [f"{choice} 3, 1"]
 116             print(lst)
 117             initial_regs = [0] * 32
 118             initial_regs[1] = random.randint(0, (1 << 64)-1)
 119             self.run_tst_program(Program(lst), initial_regs)
 120
 121     def test_parity(self):
 122         insns = ["prtyw", "prtyd"]
 123         for i in range(10):
 124             choice = random.choice(insns)
 125             lst = [f"{choice} 3, 1"]
 126             print(lst)
 127             initial_regs = [0] * 32
 128             initial_regs[1] = random.randint(0, (1 << 64)-1)
 129             self.run_tst_program(Program(lst), initial_regs)
 130
 131     def test_popcnt(self):
 132         insns = ["popcntb", "popcntw", "popcntd"]
 133         for i in range(10):
 134             choice = random.choice(insns)
 135             lst = [f"{choice} 3, 1"]
 136             print(lst)
 137             initial_regs = [0] * 32
 138             initial_regs[1] = random.randint(0, (1 << 64)-1)
 139             self.run_tst_program(Program(lst), initial_regs)
 140
 141     def test_popcnt_edge(self):
 142         insns = ["popcntb", "popcntw", "popcntd"]
 143         for choice in insns:
 144             lst = [f"{choice} 3, 1"]
 145             initial_regs = [0] * 32
 146             initial_regs[1] = -1
 147             self.run_tst_program(Program(lst), initial_regs)
 148
 149     def test_cmpb(self):
 150         lst = ["cmpb 3, 1, 2"]
 151         initial_regs = [0] * 32
 152         initial_regs[1] = 0xdeadbeefcafec0de
 153         initial_regs[2] = 0xd0adb0000afec1de
 154         self.run_tst_program(Program(lst), initial_regs)
 155
 156     def test_bpermd(self):
 157         lst = ["bpermd 3, 1, 2"]
 158         for i in range(20):
 159             initial_regs = [0] * 32
 160             initial_regs[1] = 1<<random.randint(0,63)
 161             initial_regs[2] = 0xdeadbeefcafec0de
 162             self.run_tst_program(Program(lst), initial_regs)
 163
 164     def test_ilang(self):
 165         pspec = LogicalPipeSpec(id_wid=2)
 166         alu = LogicalBasePipe(pspec)
 167         vl = rtlil.convert(alu, ports=alu.ports())
 168         with open("logical_pipeline.il", "w") as f:
 169             f.write(vl)
 170
 171
 172 class TestRunner(FHDLTestCase):
 173     def __init__(self, test_data):
 174         super().__init__("run_all")
 175         self.test_data = test_data
 176
 177     def run_all(self):
 178         m = Module()
 179         comb = m.d.comb
 180         instruction = Signal(32)
 181
 182         pdecode = create_pdecode()
 183
 184         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 185
 186         pspec = LogicalPipeSpec(id_wid=2)
 187         m.submodules.alu = alu = LogicalBasePipe(pspec)
 188
 189         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 190         comb += alu.p.valid_i.eq(1)
 191         comb += alu.n.ready_i.eq(1)
 192         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 193         sim = Simulator(m)
 194
 195         sim.add_clock(1e-6)
 196
 197         def process():
 198             for test in self.test_data:
 199                 print(test.name)
 200                 program = test.program
 201                 self.subTest(test.name)
 202                 simulator = ISA(pdecode2, test.regs, test.sprs, 0)
 203                 gen = program.generate_instructions()
 204                 instructions = list(zip(gen, program.assembly.splitlines()))
 205
 206                 index = simulator.pc.CIA.value//4
 207                 while index < len(instructions):
 208                     ins, code = instructions[index]
 209
 210                     print("0x{:X}".format(ins & 0xffffffff))
 211                     print(code)
 212
 213                     # ask the decoder to decode this binary data (endian'd)
 214                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 215                     yield instruction.eq(ins)          # raw binary instr.
 216                     yield Settle()
 217                     fn_unit = yield pdecode2.e.fn_unit
 218                     self.assertEqual(fn_unit, Function.LOGICAL.value, code)
 219                     yield from set_alu_inputs(alu, pdecode2, simulator)
 220                     yield
 221                     opname = code.split(' ')[0]
 222                     yield from simulator.call(opname)
 223                     index = simulator.pc.CIA.value//4
 224
 225                     vld = yield alu.n.valid_o
 226                     while not vld:
 227                         yield
 228                         vld = yield alu.n.valid_o
 229                     yield
 230                     alu_out = yield alu.n.data_o.o.data
 231                     out_reg_valid = yield pdecode2.e.write_reg.ok
 232                     if out_reg_valid:
 233                         write_reg_idx = yield pdecode2.e.write_reg.data
 234                         expected = simulator.gpr(write_reg_idx).value
 235                         print(f"expected {expected:x}, actual: {alu_out:x}")
 236                         self.assertEqual(expected, alu_out, code)
 237                     yield from self.check_extra_alu_outputs(alu, pdecode2,
 238                                                             simulator, code)
 239
 240         sim.add_sync_process(process)
 241         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
 242                            traces=[]):
 243             sim.run()
 244
 245     def check_extra_alu_outputs(self, alu, dec2, sim, code):
 246         rc = yield dec2.e.rc.data
 247         if rc:
 248             cr_expected = sim.crl[0].get_range().value
 249             cr_actual = yield alu.n.data_o.cr0.data
 250             self.assertEqual(cr_expected, cr_actual, code)
 251
 252
 253 if __name__ == "__main__":
 254     unittest.main(exit=False)
 255     suite = unittest.TestSuite()
 256     suite.addTest(TestRunner(LogicalTestCase.test_data))
 257
 258     runner = unittest.TextTestRunner()
 259     runner.run(suite)