1 from nmigen
import Module
, Signal
2 from soc
.simple
.test
.test_issuer
import TestRunner
3 from soc
.simulator
.program
import Program
4 from soc
.config
.endian
import bigendian
7 from soc
.fu
.test
.common
import (
8 TestAccumulatorBase
, skip_case
, TestCase
, ALUHelpers
)
10 # this test case takes about half a minute to run on my Talos II
11 class MMUDataPathTestCase(TestAccumulatorBase
):
12 # MMU on microwatt handles MTSPR, MFSPR, DCBZ and TLBIE.
13 # libre-soc has own SPR unit
14 # other instructions here -> must be load/store
16 def case_mfspr_after_invalid_load(self
):
18 "tlbie 0,0,0,0,0", # RB,RS,RIC,PRS,R
22 initial_regs
= [0] * 32
24 #FIXME initial_sprs = {'DSISR': 0x12345678, 'DAR': 0x87654321}
26 self
.add_case(Program(lst
, bigendian
),
27 initial_regs
, initial_sprs
)
30 if __name__
== "__main__":
31 unittest
.main(exit
=False)
32 suite
= unittest
.TestSuite()
33 suite
.addTest(TestRunner(MMUDataPathTestCase().test_data
,microwatt_mmu
=True))
35 runner
= unittest
.TextTestRunner()