1 from soc
.fu
.mul
.mul_input_record
import CompMULOpSubset
2 from soc
.fu
.pipe_data
import FUBaseData
, CommonPipeSpec
3 from soc
.fu
.div
.pipe_data
import DivInputData
, DivMulOutputData
4 from nmigen
import Signal
7 class MulIntermediateData(DivInputData
):
8 def __init__(self
, pspec
):
9 super().__init
__(pspec
)
11 self
.neg_res
= Signal(reset_less
=True)
12 self
.neg_res32
= Signal(reset_less
=True)
13 self
.data
.append(self
.neg_res
)
14 self
.data
.append(self
.neg_res32
)
17 class MulOutputData(FUBaseData
):
18 def __init__(self
, pspec
):
19 super().__init
__(pspec
, False) # still input style
21 self
.neg_res
= Signal(reset_less
=True)
22 self
.neg_res32
= Signal(reset_less
=True)
23 self
.data
.append(self
.neg_res
)
24 self
.data
.append(self
.neg_res32
)
28 return [('INT', 'o', "0:%d" % (self
.pspec
.XLEN
)),
29 ('XER', 'xer_so', '32')] # XER bit 32: SO
32 class MulPipeSpec(CommonPipeSpec
):
33 regspecklses
= (DivInputData
, DivMulOutputData
)
34 opsubsetkls
= CompMULOpSubset