src/soc/fu/mul/pre_stage.py

   1 # This stage is intended to do most of the work of executing multiply
   2 from nmigen import (Module, Signal, Mux)
   3 from nmutil.pipemodbase import PipeModBase
   4 from soc.fu.alu.pipe_data import ALUInputData
   5 from soc.fu.mul.pipe_data import MulIntermediateData
   6 from ieee754.part.partsig import PartitionedSignal
   7 from nmutil.util import eq32
   8
   9 class MulMainStage1(PipeModBase):
  10     def __init__(self, pspec):
  11         super().__init__(pspec, "mul1")
  12
  13     def ispec(self):
  14         return ALUInputData(self.pspec) # defines pipeline stage input format
  15
  16     def ospec(self):
  17         return MulIntermediateData(self.pspec) # pipeline stage output format
  18
  19     def elaborate(self, platform):
  20         m = Module()
  21         comb = m.d.comb
  22
  23         # convenience variables
  24         a, b, op = self.i.a, self.i.b, self.i.ctx.op
  25         a_o, b_o, neg_res_o = self.o.a, self.o.b, self.o.neg_res
  26         neg_res_o, neg_res32_o = self.o.neg_res, self.o.neg_res32
  27
  28         # check if op is 32-bit, and get sign bit from operand a
  29         is_32bit = Signal(reset_less=True)
  30         sign_a = Signal(reset_less=True)
  31         sign_b = Signal(reset_less=True)
  32         sign32_a = Signal(reset_less=True)
  33         sign32_b = Signal(reset_less=True)
  34         comb += is_32bit.eq(op.is_32bit)
  35
  36         # work out if a/b are negative (check 32-bit / signed)
  37         comb += sign_a.eq(Mux(op.is_32bit, a[31], a[63]) & op.is_signed)
  38         comb += sign_b.eq(Mux(op.is_32bit, b[31], b[63]) & op.is_signed)
  39         comb += sign32_a.eq(a[31] & op.is_signed)
  40         comb += sign32_b.eq(b[31] & op.is_signed)
  41
  42         # work out if result is negative sign
  43         comb += neg_res_o.eq(sign_a ^ sign_b)
  44         comb += neg_res32_o.eq(sign32_a ^ sign32_b) # pass through for OV32
  45
  46         # negation of a 64-bit value produces the same lower 32-bit
  47         # result as negation of just the lower 32-bits, so we don't
  48         # need to do anything special before negating
  49         abs_a = Signal(64, reset_less=True)
  50         abs_b = Signal(64, reset_less=True)
  51         comb += abs_a.eq(Mux(sign_a, -a, a))
  52         comb += abs_b.eq(Mux(sign_b, -b, b))
  53
  54         # set up 32/64 bit inputs
  55         comb += eq32(is_32bit, a_o, abs_a)
  56         comb += eq32(is_32bit, b_o, abs_b)
  57
  58         ###### XER and context, both pass-through #####
  59
  60         comb += self.o.xer_ca.eq(self.i.xer_ca)
  61         comb += self.o.xer_so.eq(self.i.xer_so)
  62         comb += self.o.ctx.eq(self.i.ctx)
  63
  64         return m
  65