src/soc/fu/shift_rot/pipe_data.py

   1 from nmigen import Signal, Const
   2 from nmutil.dynamicpipe import SimpleHandshakeRedir
   3 from soc.fu.alu.alu_input_record import CompALUOpSubset
   4 from ieee754.fpcommon.getop import FPPipeContext
   5 from soc.fu.alu.pipe_data import IntegerData
   6
   7
   8 class ShiftRotInputData(IntegerData):
   9     regspec = [('INT', 'ra', '0:63'),
  10                ('INT', 'rs', '0:63'),
  11                ('INT', 'rb', '0:63'),
  12                ('XER', 'xer_so', '32'),
  13                ('XER', 'xer_ca', '34,45')]
  14     def __init__(self, pspec):
  15         super().__init__(pspec)
  16         self.ra = Signal(64, reset_less=True) # RA
  17         self.rs = Signal(64, reset_less=True) # RS
  18         self.rb = Signal(64, reset_less=True) # RB/immediate
  19         self.xer_so = Signal(reset_less=True)    # XER bit 32: SO
  20         self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
  21
  22     def __iter__(self):
  23         yield from super().__iter__()
  24         yield self.ra
  25         yield self.rs
  26         yield self.rb
  27         yield self.xer_ca
  28         yield self.xer_so
  29
  30     def eq(self, i):
  31         lst = super().eq(i)
  32         return lst + [self.rs.eq(i.rs), self.ra.eq(i.ra),
  33                       self.rb.eq(i.rb),
  34                       self.xer_ca.eq(i.xer_ca),
  35                       self.xer_so.eq(i.xer_so)]