src/soc/fu/shift_rot/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function, CryIn)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.fu.test.common import TestCase, ALUHelpers
  16 from soc.fu.shift_rot.pipeline import ShiftRotBasePipe
  17 from soc.fu.alu.alu_input_record import CompALUOpSubset
  18 from soc.fu.shift_rot.pipe_data import ShiftRotPipeSpec
  19 import random
  20
  21
  22 def get_cu_inputs(dec2, sim):
  23     """naming (res) must conform to ShiftRotFunctionUnit input regspec
  24     """
  25     res = {}
  26
  27     # RA
  28     reg1_ok = yield dec2.e.read_reg1.ok
  29     if reg1_ok:
  30         data1 = yield dec2.e.read_reg1.data
  31         res['ra'] = sim.gpr(data1).value
  32
  33     # RB
  34     reg2_ok = yield dec2.e.read_reg2.ok
  35     if reg2_ok:
  36         data2 = yield dec2.e.read_reg2.data
  37         res['rb'] = sim.gpr(data2).value
  38
  39     # RS (RC)
  40     reg3_ok = yield dec2.e.read_reg3.ok
  41     if reg3_ok:
  42         data3 = yield dec2.e.read_reg3.data
  43         res['rc'] = sim.gpr(data3).value
  44
  45     # XER.ca
  46     cry_in = yield dec2.e.input_carry
  47     if cry_in == CryIn.CA.value:
  48         carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  49         carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
  50         res['xer_ca'] = carry | (carry32<<1)
  51
  52     print ("inputs", res)
  53
  54     return res
  55
  56
  57 def set_alu_inputs(alu, dec2, sim):
  58     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  59     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  60     # and place it into data_i.b
  61
  62     inp = yield from get_cu_inputs(dec2, sim)
  63     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  64     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
  65     yield from ALUHelpers.set_int_rc(alu, dec2, inp)
  66     yield from ALUHelpers.set_xer_ca(alu, dec2, inp)
  67
  68
  69 # This test bench is a bit different than is usual. Initially when I
  70 # was writing it, I had all of the tests call a function to create a
  71 # device under test and simulator, initialize the dut, run the
  72 # simulation for ~2 cycles, and assert that the dut output what it
  73 # should have. However, this was really slow, since it needed to
  74 # create and tear down the dut and simulator for every test case.
  75
  76 # Now, instead of doing that, every test case in ShiftRotTestCase puts some
  77 # data into the test_data list below, describing the instructions to
  78 # be tested and the initial state. Once all the tests have been run,
  79 # test_data gets passed to TestRunner which then sets up the DUT and
  80 # simulator once, runs all the data through it, and asserts that the
  81 # results match the pseudocode sim at every cycle.
  82
  83 # By doing this, I've reduced the time it takes to run the test suite
  84 # massively. Before, it took around 1 minute on my computer, now it
  85 # takes around 3 seconds
  86
  87
  88 class ShiftRotTestCase(FHDLTestCase):
  89     test_data = []
  90     def __init__(self, name):
  91         super().__init__(name)
  92         self.test_name = name
  93
  94     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
  95         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
  96         self.test_data.append(tc)
  97
  98     def test_shift(self):
  99         insns = ["slw", "sld", "srw", "srd", "sraw", "srad"]
 100         for i in range(20):
 101             choice = random.choice(insns)
 102             lst = [f"{choice} 3, 1, 2"]
 103             initial_regs = [0] * 32
 104             initial_regs[1] = random.randint(0, (1<<64)-1)
 105             initial_regs[2] = random.randint(0, 63)
 106             print(initial_regs[1], initial_regs[2])
 107             self.run_tst_program(Program(lst), initial_regs)
 108
 109     def test_shift_arith(self):
 110         lst = ["sraw 3, 1, 2"]
 111         initial_regs = [0] * 32
 112         initial_regs[1] = random.randint(0, (1<<64)-1)
 113         initial_regs[2] = random.randint(0, 63)
 114         print(initial_regs[1], initial_regs[2])
 115         self.run_tst_program(Program(lst), initial_regs)
 116
 117     def test_shift_once(self):
 118         lst = ["slw 3, 1, 4",
 119                "slw 3, 1, 2"]
 120         initial_regs = [0] * 32
 121         initial_regs[1] = 0x80000000
 122         initial_regs[2] = 0x40
 123         initial_regs[4] = 0x00
 124         self.run_tst_program(Program(lst), initial_regs)
 125
 126     def test_rlwinm(self):
 127         for i in range(10):
 128             mb = random.randint(0,31)
 129             me = random.randint(0,31)
 130             sh = random.randint(0,31)
 131             lst = [f"rlwinm 3, 1, {mb}, {me}, {sh}",
 132                    #f"rlwinm. 3, 1, {mb}, {me}, {sh}"
 133                    ]
 134             initial_regs = [0] * 32
 135             initial_regs[1] = random.randint(0, (1<<64)-1)
 136             self.run_tst_program(Program(lst), initial_regs)
 137
 138     def test_rlwimi(self):
 139         lst = ["rlwimi 3, 1, 5, 20, 6"]
 140         initial_regs = [0] * 32
 141         initial_regs[1] = 0xdeadbeef
 142         initial_regs[3] = 0x12345678
 143         self.run_tst_program(Program(lst), initial_regs)
 144
 145     def test_rlwnm(self):
 146         lst = ["rlwnm 3, 1, 2, 20, 6"]
 147         initial_regs = [0] * 32
 148         initial_regs[1] = random.randint(0, (1<<64)-1)
 149         initial_regs[2] = random.randint(0, 63)
 150         self.run_tst_program(Program(lst), initial_regs)
 151
 152     def test_rldicl(self):
 153         lst = ["rldicl 3, 1, 5, 20"]
 154         initial_regs = [0] * 32
 155         initial_regs[1] = random.randint(0, (1<<64)-1)
 156         self.run_tst_program(Program(lst), initial_regs)
 157
 158     def test_rldicr(self):
 159         lst = ["rldicr 3, 1, 5, 20"]
 160         initial_regs = [0] * 32
 161         initial_regs[1] = random.randint(0, (1<<64)-1)
 162         self.run_tst_program(Program(lst), initial_regs)
 163
 164     def test_rlc(self):
 165         insns = ["rldic", "rldicl", "rldicr"]
 166         for i in range(20):
 167             choice = random.choice(insns)
 168             sh = random.randint(0, 63)
 169             m = random.randint(0, 63)
 170             lst = [f"{choice} 3, 1, {sh}, {m}"]
 171             initial_regs = [0] * 32
 172             initial_regs[1] = random.randint(0, (1<<64)-1)
 173             self.run_tst_program(Program(lst), initial_regs)
 174
 175     def test_ilang(self):
 176         pspec = ShiftRotPipeSpec(id_wid=2)
 177         alu = ShiftRotBasePipe(pspec)
 178         vl = rtlil.convert(alu, ports=alu.ports())
 179         with open("pipeline.il", "w") as f:
 180             f.write(vl)
 181
 182
 183 class TestRunner(FHDLTestCase):
 184     def __init__(self, test_data):
 185         super().__init__("run_all")
 186         self.test_data = test_data
 187
 188     def run_all(self):
 189         m = Module()
 190         comb = m.d.comb
 191         instruction = Signal(32)
 192
 193         pdecode = create_pdecode()
 194
 195         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 196
 197         pspec = ShiftRotPipeSpec(id_wid=2)
 198         m.submodules.alu = alu = ShiftRotBasePipe(pspec)
 199
 200         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 201         comb += alu.p.valid_i.eq(1)
 202         comb += alu.n.ready_i.eq(1)
 203         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 204         sim = Simulator(m)
 205
 206         sim.add_clock(1e-6)
 207         def process():
 208             for test in self.test_data:
 209                 print(test.name)
 210                 program = test.program
 211                 self.subTest(test.name)
 212                 simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
 213                                 test.mem, test.msr)
 214                 gen = program.generate_instructions()
 215                 instructions = list(zip(gen, program.assembly.splitlines()))
 216
 217                 index = simulator.pc.CIA.value//4
 218                 while index < len(instructions):
 219                     ins, code = instructions[index]
 220
 221                     print("0x{:X}".format(ins & 0xffffffff))
 222                     print(code)
 223
 224                     # ask the decoder to decode this binary data (endian'd)
 225                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 226                     yield instruction.eq(ins)          # raw binary instr.
 227                     yield Settle()
 228                     fn_unit = yield pdecode2.e.fn_unit
 229                     self.assertEqual(fn_unit, Function.SHIFT_ROT.value)
 230                     yield from set_alu_inputs(alu, pdecode2, simulator)
 231                     yield
 232                     opname = code.split(' ')[0]
 233                     yield from simulator.call(opname)
 234                     index = simulator.pc.CIA.value//4
 235
 236                     vld = yield alu.n.valid_o
 237                     while not vld:
 238                         yield
 239                         vld = yield alu.n.valid_o
 240                     yield
 241                     alu_out = yield alu.n.data_o.o.data
 242                     out_reg_valid = yield pdecode2.e.write_reg.ok
 243                     if out_reg_valid:
 244                         write_reg_idx = yield pdecode2.e.write_reg.data
 245                         expected = simulator.gpr(write_reg_idx).value
 246                         msg = f"expected {expected:x}, actual: {alu_out:x}"
 247                         self.assertEqual(expected, alu_out, msg)
 248                     yield from self.check_extra_alu_outputs(alu, pdecode2,
 249                                                             simulator, code)
 250                     break
 251
 252         sim.add_sync_process(process)
 253         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
 254                             traces=[]):
 255             sim.run()
 256
 257     def check_extra_alu_outputs(self, alu, dec2, sim, code):
 258         rc = yield dec2.e.rc.data
 259         if rc:
 260             cr_expected = sim.crl[0].get_range().value
 261             cr_actual = yield alu.n.data_o.cr0
 262             self.assertEqual(cr_expected, cr_actual, code)
 263
 264         cry_out = yield dec2.e.output_carry
 265         if cry_out:
 266             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 267             real_carry = yield alu.n.data_o.xer_ca.data[0] # XXX CO not CO32
 268             self.assertEqual(expected_carry, real_carry, code)
 269             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 270             real_carry32 = yield alu.n.data_o.xer_ca.data[1] # XXX CO32
 271             self.assertEqual(expected_carry32, real_carry32, code)
 272
 273
 274
 275 if __name__ == "__main__":
 276     unittest.main(exit=False)
 277     suite = unittest.TestSuite()
 278     suite.addTest(TestRunner(ShiftRotTestCase.test_data))
 279
 280     runner = unittest.TextTestRunner()
 281     runner.run(suite)