1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmigen
.test
.utils
import FHDLTestCase
4 from nmigen
.cli
import rtlil
6 from soc
.decoder
.isa
.caller
import ISACaller
, special_sprs
7 from soc
.decoder
.power_decoder
import (create_pdecode
)
8 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
9 from soc
.decoder
.power_enums
import (XER_bits
, Function
, CryIn
)
10 from soc
.decoder
.selectable_int
import SelectableInt
11 from soc
.simulator
.program
import Program
12 from soc
.decoder
.isa
.all
import ISA
15 from soc
.fu
.shift_rot
.pipeline
import ShiftRotBasePipe
16 from soc
.fu
.alu
.alu_input_record
import CompALUOpSubset
17 from soc
.fu
.shift_rot
.pipe_data
import ShiftRotPipeSpec
21 def __init__(self
, program
, regs
, sprs
, name
):
22 self
.program
= program
28 def get_cu_inputs(dec2
, sim
):
29 """naming (res) must conform to ShiftRotFunctionUnit input regspec
34 reg1_ok
= yield dec2
.e
.read_reg1
.ok
36 data1
= yield dec2
.e
.read_reg1
.data
37 res
['ra'] = sim
.gpr(data1
).value
40 reg2_ok
= yield dec2
.e
.read_reg2
.ok
42 data2
= yield dec2
.e
.read_reg2
.data
43 res
['rb'] = sim
.gpr(data2
).value
46 reg3_ok
= yield dec2
.e
.read_reg3
.ok
48 data3
= yield dec2
.e
.read_reg3
.data
49 res
['rc'] = sim
.gpr(data3
).value
52 cry_in
= yield dec2
.e
.input_carry
53 if cry_in
== CryIn
.CA
.value
:
54 carry
= 1 if sim
.spr
['XER'][XER_bits
['CA']] else 0
55 carry32
= 1 if sim
.spr
['XER'][XER_bits
['CA32']] else 0
56 res
['xer_ca'] = carry |
(carry32
<<1)
63 def set_alu_inputs(alu
, dec2
, sim
):
64 # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
65 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
66 # and place it into data_i.b
68 inp
= yield from get_cu_inputs(dec2
, sim
)
70 yield alu
.p
.data_i
.a
.eq(inp
['ra'])
72 yield alu
.p
.data_i
.a
.eq(0)
74 yield alu
.p
.data_i
.rb
.eq(inp
['rb'])
76 yield alu
.p
.data_i
.rb
.eq(0)
78 yield alu
.p
.data_i
.rs
.eq(inp
['rc'])
80 yield alu
.p
.data_i
.rs
.eq(0)
82 # If there's an immediate, set the B operand to that
83 imm_ok
= yield dec2
.e
.imm_data
.imm_ok
85 data2
= yield dec2
.e
.imm_data
.imm
86 yield alu
.p
.data_i
.rb
.eq(data2
)
89 yield alu
.p
.data_i
.xer_ca
.eq(inp
['xer_ca'])
90 print ("extra inputs: CA/32", bin(inp
['xer_ca']))
92 yield alu
.p
.data_i
.xer_ca
.eq(0)
95 # This test bench is a bit different than is usual. Initially when I
96 # was writing it, I had all of the tests call a function to create a
97 # device under test and simulator, initialize the dut, run the
98 # simulation for ~2 cycles, and assert that the dut output what it
99 # should have. However, this was really slow, since it needed to
100 # create and tear down the dut and simulator for every test case.
102 # Now, instead of doing that, every test case in ShiftRotTestCase puts some
103 # data into the test_data list below, describing the instructions to
104 # be tested and the initial state. Once all the tests have been run,
105 # test_data gets passed to TestRunner which then sets up the DUT and
106 # simulator once, runs all the data through it, and asserts that the
107 # results match the pseudocode sim at every cycle.
109 # By doing this, I've reduced the time it takes to run the test suite
110 # massively. Before, it took around 1 minute on my computer, now it
111 # takes around 3 seconds
116 class ShiftRotTestCase(FHDLTestCase
):
117 def __init__(self
, name
):
118 super().__init
__(name
)
119 self
.test_name
= name
120 def run_tst_program(self
, prog
, initial_regs
=[0] * 32, initial_sprs
={}):
121 tc
= TestCase(prog
, initial_regs
, initial_sprs
, self
.test_name
)
125 def test_shift(self
):
126 insns
= ["slw", "sld", "srw", "srd", "sraw", "srad"]
128 choice
= random
.choice(insns
)
129 lst
= [f
"{choice} 3, 1, 2"]
130 initial_regs
= [0] * 32
131 initial_regs
[1] = random
.randint(0, (1<<64)-1)
132 initial_regs
[2] = random
.randint(0, 63)
133 print(initial_regs
[1], initial_regs
[2])
134 self
.run_tst_program(Program(lst
), initial_regs
)
137 def test_shift_arith(self
):
138 lst
= ["sraw 3, 1, 2"]
139 initial_regs
= [0] * 32
140 initial_regs
[1] = random
.randint(0, (1<<64)-1)
141 initial_regs
[2] = random
.randint(0, 63)
142 print(initial_regs
[1], initial_regs
[2])
143 self
.run_tst_program(Program(lst
), initial_regs
)
145 def test_shift_once(self
):
146 lst
= ["slw 3, 1, 4",
148 initial_regs
= [0] * 32
149 initial_regs
[1] = 0x80000000
150 initial_regs
[2] = 0x40
151 initial_regs
[4] = 0x00
152 self
.run_tst_program(Program(lst
), initial_regs
)
154 def test_rlwinm(self
):
156 mb
= random
.randint(0,31)
157 me
= random
.randint(0,31)
158 sh
= random
.randint(0,31)
159 lst
= [f
"rlwinm 3, 1, {mb}, {me}, {sh}",
160 #f"rlwinm. 3, 1, {mb}, {me}, {sh}"
162 initial_regs
= [0] * 32
163 initial_regs
[1] = random
.randint(0, (1<<64)-1)
164 self
.run_tst_program(Program(lst
), initial_regs
)
166 def test_rlwimi(self
):
167 lst
= ["rlwimi 3, 1, 5, 20, 6"]
168 initial_regs
= [0] * 32
169 initial_regs
[1] = 0xdeadbeef
170 initial_regs
[3] = 0x12345678
171 self
.run_tst_program(Program(lst
), initial_regs
)
173 def test_rlwnm(self
):
174 lst
= ["rlwnm 3, 1, 2, 20, 6"]
175 initial_regs
= [0] * 32
176 initial_regs
[1] = random
.randint(0, (1<<64)-1)
177 initial_regs
[2] = random
.randint(0, 63)
178 self
.run_tst_program(Program(lst
), initial_regs
)
180 def test_rldicl(self
):
181 lst
= ["rldicl 3, 1, 5, 20"]
182 initial_regs
= [0] * 32
183 initial_regs
[1] = random
.randint(0, (1<<64)-1)
184 self
.run_tst_program(Program(lst
), initial_regs
)
186 def test_rldicr(self
):
187 lst
= ["rldicr 3, 1, 5, 20"]
188 initial_regs
= [0] * 32
189 initial_regs
[1] = random
.randint(0, (1<<64)-1)
190 self
.run_tst_program(Program(lst
), initial_regs
)
193 insns
= ["rldic", "rldicl", "rldicr"]
195 choice
= random
.choice(insns
)
196 sh
= random
.randint(0, 63)
197 m
= random
.randint(0, 63)
198 lst
= [f
"{choice} 3, 1, {sh}, {m}"]
199 initial_regs
= [0] * 32
200 initial_regs
[1] = random
.randint(0, (1<<64)-1)
201 self
.run_tst_program(Program(lst
), initial_regs
)
203 def test_ilang(self
):
204 pspec
= ShiftRotPipeSpec(id_wid
=2)
205 alu
= ShiftRotBasePipe(pspec
)
206 vl
= rtlil
.convert(alu
, ports
=alu
.ports())
207 with
open("pipeline.il", "w") as f
:
211 class TestRunner(FHDLTestCase
):
212 def __init__(self
, test_data
):
213 super().__init
__("run_all")
214 self
.test_data
= test_data
219 instruction
= Signal(32)
221 pdecode
= create_pdecode()
223 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
225 pspec
= ShiftRotPipeSpec(id_wid
=2)
226 m
.submodules
.alu
= alu
= ShiftRotBasePipe(pspec
)
228 comb
+= alu
.p
.data_i
.ctx
.op
.eq_from_execute1(pdecode2
.e
)
229 comb
+= alu
.p
.valid_i
.eq(1)
230 comb
+= alu
.n
.ready_i
.eq(1)
231 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
236 for test
in self
.test_data
:
238 program
= test
.program
239 self
.subTest(test
.name
)
240 simulator
= ISA(pdecode2
, test
.regs
, test
.sprs
, 0)
241 gen
= program
.generate_instructions()
242 instructions
= list(zip(gen
, program
.assembly
.splitlines()))
244 index
= simulator
.pc
.CIA
.value
//4
245 while index
< len(instructions
):
246 ins
, code
= instructions
[index
]
248 print("0x{:X}".format(ins
& 0xffffffff))
251 # ask the decoder to decode this binary data (endian'd)
252 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
253 yield instruction
.eq(ins
) # raw binary instr.
255 fn_unit
= yield pdecode2
.e
.fn_unit
256 self
.assertEqual(fn_unit
, Function
.SHIFT_ROT
.value
)
257 yield from set_alu_inputs(alu
, pdecode2
, simulator
)
259 opname
= code
.split(' ')[0]
260 yield from simulator
.call(opname
)
261 index
= simulator
.pc
.CIA
.value
//4
263 vld
= yield alu
.n
.valid_o
266 vld
= yield alu
.n
.valid_o
268 alu_out
= yield alu
.n
.data_o
.o
.data
269 out_reg_valid
= yield pdecode2
.e
.write_reg
.ok
271 write_reg_idx
= yield pdecode2
.e
.write_reg
.data
272 expected
= simulator
.gpr(write_reg_idx
).value
273 msg
= f
"expected {expected:x}, actual: {alu_out:x}"
274 self
.assertEqual(expected
, alu_out
, msg
)
275 yield from self
.check_extra_alu_outputs(alu
, pdecode2
,
279 sim
.add_sync_process(process
)
280 with sim
.write_vcd("simulator.vcd", "simulator.gtkw",
284 def check_extra_alu_outputs(self
, alu
, dec2
, sim
):
285 rc
= yield dec2
.e
.rc
.data
287 cr_expected
= sim
.crl
[0].get_range().value
288 cr_actual
= yield alu
.n
.data_o
.cr0
289 self
.assertEqual(cr_expected
, cr_actual
)
292 if __name__
== "__main__":
293 unittest
.main(exit
=False)
294 suite
= unittest
.TestSuite()
295 suite
.addTest(TestRunner(test_data
))
297 runner
= unittest
.TextTestRunner()