src/soc/fu/shift_rot/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function, CryIn)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.fu.test.common import TestCase, ALUHelpers
  16 from soc.fu.shift_rot.pipeline import ShiftRotBasePipe
  17 from soc.fu.alu.alu_input_record import CompALUOpSubset
  18 from soc.fu.shift_rot.pipe_data import ShiftRotPipeSpec
  19 import random
  20
  21
  22 def get_cu_inputs(dec2, sim):
  23     """naming (res) must conform to ShiftRotFunctionUnit input regspec
  24     """
  25     res = {}
  26
  27     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
  28     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
  29     yield from ALUHelpers.get_sim_int_rc(res, sim, dec2) # RC
  30     yield from ALUHelpers.get_rd_sim_xer_ca(res, sim, dec2) # XER.ca
  31
  32     print ("inputs", res)
  33
  34     return res
  35
  36
  37 def set_alu_inputs(alu, dec2, sim):
  38     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  39     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  40     # and place it into data_i.b
  41
  42     inp = yield from get_cu_inputs(dec2, sim)
  43     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  44     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
  45     yield from ALUHelpers.set_int_rc(alu, dec2, inp)
  46     yield from ALUHelpers.set_xer_ca(alu, dec2, inp)
  47
  48
  49 # This test bench is a bit different than is usual. Initially when I
  50 # was writing it, I had all of the tests call a function to create a
  51 # device under test and simulator, initialize the dut, run the
  52 # simulation for ~2 cycles, and assert that the dut output what it
  53 # should have. However, this was really slow, since it needed to
  54 # create and tear down the dut and simulator for every test case.
  55
  56 # Now, instead of doing that, every test case in ShiftRotTestCase puts some
  57 # data into the test_data list below, describing the instructions to
  58 # be tested and the initial state. Once all the tests have been run,
  59 # test_data gets passed to TestRunner which then sets up the DUT and
  60 # simulator once, runs all the data through it, and asserts that the
  61 # results match the pseudocode sim at every cycle.
  62
  63 # By doing this, I've reduced the time it takes to run the test suite
  64 # massively. Before, it took around 1 minute on my computer, now it
  65 # takes around 3 seconds
  66
  67
  68 class ShiftRotTestCase(FHDLTestCase):
  69     test_data = []
  70     def __init__(self, name):
  71         super().__init__(name)
  72         self.test_name = name
  73
  74     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
  75         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
  76         self.test_data.append(tc)
  77
  78     def test_shift(self):
  79         insns = ["slw", "sld", "srw", "srd", "sraw", "srad"]
  80         for i in range(20):
  81             choice = random.choice(insns)
  82             lst = [f"{choice} 3, 1, 2"]
  83             initial_regs = [0] * 32
  84             initial_regs[1] = random.randint(0, (1<<64)-1)
  85             initial_regs[2] = random.randint(0, 63)
  86             print(initial_regs[1], initial_regs[2])
  87             self.run_tst_program(Program(lst), initial_regs)
  88
  89     def test_shift_arith(self):
  90         lst = ["sraw 3, 1, 2"]
  91         initial_regs = [0] * 32
  92         initial_regs[1] = random.randint(0, (1<<64)-1)
  93         initial_regs[2] = random.randint(0, 63)
  94         print(initial_regs[1], initial_regs[2])
  95         self.run_tst_program(Program(lst), initial_regs)
  96
  97     def test_shift_once(self):
  98         lst = ["slw 3, 1, 4",
  99                "slw 3, 1, 2"]
 100         initial_regs = [0] * 32
 101         initial_regs[1] = 0x80000000
 102         initial_regs[2] = 0x40
 103         initial_regs[4] = 0x00
 104         self.run_tst_program(Program(lst), initial_regs)
 105
 106     def test_rlwinm(self):
 107         for i in range(10):
 108             mb = random.randint(0,31)
 109             me = random.randint(0,31)
 110             sh = random.randint(0,31)
 111             lst = [f"rlwinm 3, 1, {mb}, {me}, {sh}",
 112                    #f"rlwinm. 3, 1, {mb}, {me}, {sh}"
 113                    ]
 114             initial_regs = [0] * 32
 115             initial_regs[1] = random.randint(0, (1<<64)-1)
 116             self.run_tst_program(Program(lst), initial_regs)
 117
 118     def test_rlwimi(self):
 119         lst = ["rlwimi 3, 1, 5, 20, 6"]
 120         initial_regs = [0] * 32
 121         initial_regs[1] = 0xdeadbeef
 122         initial_regs[3] = 0x12345678
 123         self.run_tst_program(Program(lst), initial_regs)
 124
 125     def test_rlwnm(self):
 126         lst = ["rlwnm 3, 1, 2, 20, 6"]
 127         initial_regs = [0] * 32
 128         initial_regs[1] = random.randint(0, (1<<64)-1)
 129         initial_regs[2] = random.randint(0, 63)
 130         self.run_tst_program(Program(lst), initial_regs)
 131
 132     def test_rldicl(self):
 133         lst = ["rldicl 3, 1, 5, 20"]
 134         initial_regs = [0] * 32
 135         initial_regs[1] = random.randint(0, (1<<64)-1)
 136         self.run_tst_program(Program(lst), initial_regs)
 137
 138     def test_rldicr(self):
 139         lst = ["rldicr 3, 1, 5, 20"]
 140         initial_regs = [0] * 32
 141         initial_regs[1] = random.randint(0, (1<<64)-1)
 142         self.run_tst_program(Program(lst), initial_regs)
 143
 144     def test_rlc(self):
 145         insns = ["rldic", "rldicl", "rldicr"]
 146         for i in range(20):
 147             choice = random.choice(insns)
 148             sh = random.randint(0, 63)
 149             m = random.randint(0, 63)
 150             lst = [f"{choice} 3, 1, {sh}, {m}"]
 151             initial_regs = [0] * 32
 152             initial_regs[1] = random.randint(0, (1<<64)-1)
 153             self.run_tst_program(Program(lst), initial_regs)
 154
 155     def test_ilang(self):
 156         pspec = ShiftRotPipeSpec(id_wid=2)
 157         alu = ShiftRotBasePipe(pspec)
 158         vl = rtlil.convert(alu, ports=alu.ports())
 159         with open("pipeline.il", "w") as f:
 160             f.write(vl)
 161
 162
 163 class TestRunner(FHDLTestCase):
 164     def __init__(self, test_data):
 165         super().__init__("run_all")
 166         self.test_data = test_data
 167
 168     def run_all(self):
 169         m = Module()
 170         comb = m.d.comb
 171         instruction = Signal(32)
 172
 173         pdecode = create_pdecode()
 174
 175         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 176
 177         pspec = ShiftRotPipeSpec(id_wid=2)
 178         m.submodules.alu = alu = ShiftRotBasePipe(pspec)
 179
 180         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 181         comb += alu.p.valid_i.eq(1)
 182         comb += alu.n.ready_i.eq(1)
 183         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 184         sim = Simulator(m)
 185
 186         sim.add_clock(1e-6)
 187         def process():
 188             for test in self.test_data:
 189                 print(test.name)
 190                 program = test.program
 191                 self.subTest(test.name)
 192                 simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
 193                                 test.mem, test.msr)
 194                 gen = program.generate_instructions()
 195                 instructions = list(zip(gen, program.assembly.splitlines()))
 196
 197                 index = simulator.pc.CIA.value//4
 198                 while index < len(instructions):
 199                     ins, code = instructions[index]
 200
 201                     print("0x{:X}".format(ins & 0xffffffff))
 202                     print(code)
 203
 204                     # ask the decoder to decode this binary data (endian'd)
 205                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 206                     yield instruction.eq(ins)          # raw binary instr.
 207                     yield Settle()
 208                     fn_unit = yield pdecode2.e.do.fn_unit
 209                     self.assertEqual(fn_unit, Function.SHIFT_ROT.value)
 210                     yield from set_alu_inputs(alu, pdecode2, simulator)
 211                     yield
 212                     opname = code.split(' ')[0]
 213                     yield from simulator.call(opname)
 214                     index = simulator.pc.CIA.value//4
 215
 216                     vld = yield alu.n.valid_o
 217                     while not vld:
 218                         yield
 219                         vld = yield alu.n.valid_o
 220                     yield
 221                     alu_out = yield alu.n.data_o.o.data
 222
 223                     yield from self.check_alu_outputs(alu, pdecode2,
 224                                                             simulator, code)
 225                     break
 226
 227         sim.add_sync_process(process)
 228         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
 229                             traces=[]):
 230             sim.run()
 231
 232     def check_alu_outputs(self, alu, dec2, sim, code):
 233
 234         rc = yield dec2.e.do.rc.data
 235         cridx_ok = yield dec2.e.write_cr.ok
 236         cridx = yield dec2.e.write_cr.data
 237
 238         print ("check extra output", repr(code), cridx_ok, cridx)
 239         if rc:
 240             self.assertEqual(cridx, 0, code)
 241
 242         sim_o = {}
 243         res = {}
 244
 245         yield from ALUHelpers.get_cr_a(res, alu, dec2)
 246         yield from ALUHelpers.get_xer_ca(res, alu, dec2)
 247         yield from ALUHelpers.get_int_o(res, alu, dec2)
 248
 249         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
 250         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 251         yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
 252
 253         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
 254         ALUHelpers.check_xer_ca(self, res, sim_o, code)
 255         ALUHelpers.check_int_o(self, res, sim_o, code)
 256
 257
 258
 259 if __name__ == "__main__":
 260     unittest.main(exit=False)
 261     suite = unittest.TestSuite()
 262     suite.addTest(TestRunner(ShiftRotTestCase.test_data))
 263
 264     runner = unittest.TextTestRunner()
 265     runner.run(suite)