1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmigen
.test
.utils
import FHDLTestCase
4 from nmigen
.cli
import rtlil
6 from soc
.decoder
.isa
.caller
import ISACaller
, special_sprs
7 from soc
.decoder
.power_decoder
import (create_pdecode
)
8 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
9 from soc
.decoder
.power_enums
import (XER_bits
, Function
)
10 from soc
.decoder
.selectable_int
import SelectableInt
11 from soc
.simulator
.program
import Program
12 from soc
.decoder
.isa
.all
import ISA
15 from soc
.fu
.shift_rot
.pipeline
import ShiftRotBasePipe
16 from soc
.fu
.alu
.alu_input_record
import CompALUOpSubset
17 from soc
.fu
.alu
.pipe_data
import ALUPipeSpec
21 def __init__(self
, program
, regs
, sprs
, name
):
22 self
.program
= program
27 def get_rec_width(rec
):
29 # Setup random inputs for dut.op
35 def set_alu_inputs(alu
, dec2
, sim
):
37 # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
38 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
39 # and place it into data_i.b
41 reg3_ok
= yield dec2
.e
.read_reg3
.ok
43 reg3_sel
= yield dec2
.e
.read_reg3
.data
44 data3
= sim
.gpr(reg3_sel
).value
47 reg1_ok
= yield dec2
.e
.read_reg1
.ok
49 reg1_sel
= yield dec2
.e
.read_reg1
.data
50 data1
= sim
.gpr(reg1_sel
).value
53 reg2_ok
= yield dec2
.e
.read_reg2
.ok
54 imm_ok
= yield dec2
.e
.imm_data
.ok
56 reg2_sel
= yield dec2
.e
.read_reg2
.data
57 data2
= sim
.gpr(reg2_sel
).value
59 data2
= yield dec2
.e
.imm_data
.imm
63 yield alu
.p
.data_i
.ra
.eq(data1
)
64 yield alu
.p
.data_i
.rb
.eq(data2
)
65 yield alu
.p
.data_i
.rs
.eq(data3
)
68 def set_extra_alu_inputs(alu
, dec2
, sim
):
69 carry
= 1 if sim
.spr
['XER'][XER_bits
['CA']] else 0
70 carry32
= 1 if sim
.spr
['XER'][XER_bits
['CA32']] else 0
71 yield alu
.p
.data_i
.xer_ca
[0].eq(carry
)
72 yield alu
.p
.data_i
.xer_ca
[1].eq(carry32
)
73 so
= 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
74 yield alu
.p
.data_i
.xer_so
.eq(so
)
77 # This test bench is a bit different than is usual. Initially when I
78 # was writing it, I had all of the tests call a function to create a
79 # device under test and simulator, initialize the dut, run the
80 # simulation for ~2 cycles, and assert that the dut output what it
81 # should have. However, this was really slow, since it needed to
82 # create and tear down the dut and simulator for every test case.
84 # Now, instead of doing that, every test case in ShiftRotTestCase puts some
85 # data into the test_data list below, describing the instructions to
86 # be tested and the initial state. Once all the tests have been run,
87 # test_data gets passed to TestRunner which then sets up the DUT and
88 # simulator once, runs all the data through it, and asserts that the
89 # results match the pseudocode sim at every cycle.
91 # By doing this, I've reduced the time it takes to run the test suite
92 # massively. Before, it took around 1 minute on my computer, now it
93 # takes around 3 seconds
98 class ShiftRotTestCase(FHDLTestCase
):
99 def __init__(self
, name
):
100 super().__init
__(name
)
101 self
.test_name
= name
102 def run_tst_program(self
, prog
, initial_regs
=[0] * 32, initial_sprs
={}):
103 tc
= TestCase(prog
, initial_regs
, initial_sprs
, self
.test_name
)
107 def test_shift(self
):
108 insns
= ["slw", "sld", "srw", "srd", "sraw", "srad"]
110 choice
= random
.choice(insns
)
111 lst
= [f
"{choice} 3, 1, 2"]
112 initial_regs
= [0] * 32
113 initial_regs
[1] = random
.randint(0, (1<<64)-1)
114 initial_regs
[2] = random
.randint(0, 63)
115 print(initial_regs
[1], initial_regs
[2])
116 self
.run_tst_program(Program(lst
), initial_regs
)
119 def test_shift_arith(self
):
120 lst
= ["sraw 3, 1, 2"]
121 initial_regs
= [0] * 32
122 initial_regs
[1] = random
.randint(0, (1<<64)-1)
123 initial_regs
[2] = random
.randint(0, 63)
124 print(initial_regs
[1], initial_regs
[2])
125 self
.run_tst_program(Program(lst
), initial_regs
)
127 def test_shift_once(self
):
128 lst
= ["slw 3, 1, 4",
130 initial_regs
= [0] * 32
131 initial_regs
[1] = 0x80000000
132 initial_regs
[2] = 0x40
133 initial_regs
[4] = 0x00
134 self
.run_tst_program(Program(lst
), initial_regs
)
136 def test_rlwinm(self
):
138 mb
= random
.randint(0,31)
139 me
= random
.randint(0,31)
140 sh
= random
.randint(0,31)
141 lst
= [f
"rlwinm 3, 1, {mb}, {me}, {sh}"]
142 initial_regs
= [0] * 32
143 initial_regs
[1] = random
.randint(0, (1<<64)-1)
144 self
.run_tst_program(Program(lst
), initial_regs
)
146 def test_rlwimi(self
):
147 lst
= ["rlwimi 3, 1, 5, 20, 6"]
148 initial_regs
= [0] * 32
149 initial_regs
[1] = 0xdeadbeef
150 initial_regs
[3] = 0x12345678
151 self
.run_tst_program(Program(lst
), initial_regs
)
153 def test_rlwnm(self
):
154 lst
= ["rlwnm 3, 1, 2, 20, 6"]
155 initial_regs
= [0] * 32
156 initial_regs
[1] = random
.randint(0, (1<<64)-1)
157 initial_regs
[2] = random
.randint(0, 63)
158 self
.run_tst_program(Program(lst
), initial_regs
)
160 def test_rldicl(self
):
161 lst
= ["rldicl 3, 1, 5, 20"]
162 initial_regs
= [0] * 32
163 initial_regs
[1] = random
.randint(0, (1<<64)-1)
164 self
.run_tst_program(Program(lst
), initial_regs
)
166 def test_rldicr(self
):
167 lst
= ["rldicr 3, 1, 5, 20"]
168 initial_regs
= [0] * 32
169 initial_regs
[1] = random
.randint(0, (1<<64)-1)
170 self
.run_tst_program(Program(lst
), initial_regs
)
173 insns
= ["rldic", "rldicl", "rldicr"]
175 choice
= random
.choice(insns
)
176 sh
= random
.randint(0, 63)
177 m
= random
.randint(0, 63)
178 lst
= [f
"{choice} 3, 1, {sh}, {m}"]
179 initial_regs
= [0] * 32
180 initial_regs
[1] = random
.randint(0, (1<<64)-1)
181 self
.run_tst_program(Program(lst
), initial_regs
)
183 def test_ilang(self
):
184 rec
= CompALUOpSubset()
186 pspec
= ALUPipeSpec(id_wid
=2, op_wid
=get_rec_width(rec
))
187 alu
= ShiftRotBasePipe(pspec
)
188 vl
= rtlil
.convert(alu
, ports
=alu
.ports())
189 with
open("pipeline.il", "w") as f
:
193 class TestRunner(FHDLTestCase
):
194 def __init__(self
, test_data
):
195 super().__init
__("run_all")
196 self
.test_data
= test_data
201 instruction
= Signal(32)
203 pdecode
= create_pdecode()
205 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
207 rec
= CompALUOpSubset()
209 pspec
= ALUPipeSpec(id_wid
=2, op_wid
=get_rec_width(rec
))
210 m
.submodules
.alu
= alu
= ShiftRotBasePipe(pspec
)
212 comb
+= alu
.p
.data_i
.ctx
.op
.eq_from_execute1(pdecode2
.e
)
213 comb
+= alu
.p
.valid_i
.eq(1)
214 comb
+= alu
.n
.ready_i
.eq(1)
215 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
220 for test
in self
.test_data
:
222 program
= test
.program
223 self
.subTest(test
.name
)
224 simulator
= ISA(pdecode2
, test
.regs
, test
.sprs
, 0)
225 gen
= program
.generate_instructions()
226 instructions
= list(zip(gen
, program
.assembly
.splitlines()))
228 index
= simulator
.pc
.CIA
.value
//4
229 while index
< len(instructions
):
230 ins
, code
= instructions
[index
]
232 print("0x{:X}".format(ins
& 0xffffffff))
235 # ask the decoder to decode this binary data (endian'd)
236 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
237 yield instruction
.eq(ins
) # raw binary instr.
239 fn_unit
= yield pdecode2
.e
.fn_unit
240 self
.assertEqual(fn_unit
, Function
.SHIFT_ROT
.value
)
241 yield from set_alu_inputs(alu
, pdecode2
, simulator
)
242 yield from set_extra_alu_inputs(alu
, pdecode2
, simulator
)
244 opname
= code
.split(' ')[0]
245 yield from simulator
.call(opname
)
246 index
= simulator
.pc
.CIA
.value
//4
248 vld
= yield alu
.n
.valid_o
251 vld
= yield alu
.n
.valid_o
253 alu_out
= yield alu
.n
.data_o
.o
254 out_reg_valid
= yield pdecode2
.e
.write_reg
.ok
256 write_reg_idx
= yield pdecode2
.e
.write_reg
.data
257 expected
= simulator
.gpr(write_reg_idx
).value
258 msg
= f
"expected {expected:x}, actual: {alu_out:x}"
259 self
.assertEqual(expected
, alu_out
, msg
)
260 yield from self
.check_extra_alu_outputs(alu
, pdecode2
,
263 sim
.add_sync_process(process
)
264 with sim
.write_vcd("simulator.vcd", "simulator.gtkw",
267 def check_extra_alu_outputs(self
, alu
, dec2
, sim
):
268 rc
= yield dec2
.e
.rc
.data
270 cr_expected
= sim
.crl
[0].get_range().value
271 cr_actual
= yield alu
.n
.data_o
.cr0
272 self
.assertEqual(cr_expected
, cr_actual
)
275 if __name__
== "__main__":
276 unittest
.main(exit
=False)
277 suite
= unittest
.TestSuite()
278 suite
.addTest(TestRunner(test_data
))
280 runner
= unittest
.TextTestRunner()