src/soc/fu/shift_rot/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmigen.test.utils import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.fu.shift_rot.pipeline import ShiftRotBasePipe
  16 from soc.fu.alu.alu_input_record import CompALUOpSubset
  17 from soc.fu.shift_rot.pipe_data import ShiftRotPipeSpec
  18 import random
  19
  20 class TestCase:
  21     def __init__(self, program, regs, sprs, name):
  22         self.program = program
  23         self.regs = regs
  24         self.sprs = sprs
  25         self.name = name
  26
  27
  28 def set_alu_inputs(alu, dec2, sim):
  29     inputs = []
  30     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  31     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  32     # and place it into data_i.b
  33
  34     reg3_ok = yield dec2.e.read_reg3.ok
  35     if reg3_ok:
  36         reg3_sel = yield dec2.e.read_reg3.data
  37         data3 = sim.gpr(reg3_sel).value
  38     else:
  39         data3 = 0
  40     reg1_ok = yield dec2.e.read_reg1.ok
  41     if reg1_ok:
  42         reg1_sel = yield dec2.e.read_reg1.data
  43         data1 = sim.gpr(reg1_sel).value
  44     else:
  45         data1 = 0
  46     reg2_ok = yield dec2.e.read_reg2.ok
  47     imm_ok = yield dec2.e.imm_data.ok
  48     if reg2_ok:
  49         reg2_sel = yield dec2.e.read_reg2.data
  50         data2 = sim.gpr(reg2_sel).value
  51     elif imm_ok:
  52         data2 = yield dec2.e.imm_data.imm
  53     else:
  54         data2 = 0
  55
  56     yield alu.p.data_i.a.eq(data1)
  57     yield alu.p.data_i.rb.eq(data2)
  58     yield alu.p.data_i.rs.eq(data3)
  59
  60
  61 def set_extra_alu_inputs(alu, dec2, sim):
  62     carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  63     carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
  64     yield alu.p.data_i.xer_ca[0].eq(carry)
  65     yield alu.p.data_i.xer_ca[1].eq(carry32)
  66
  67
  68 # This test bench is a bit different than is usual. Initially when I
  69 # was writing it, I had all of the tests call a function to create a
  70 # device under test and simulator, initialize the dut, run the
  71 # simulation for ~2 cycles, and assert that the dut output what it
  72 # should have. However, this was really slow, since it needed to
  73 # create and tear down the dut and simulator for every test case.
  74
  75 # Now, instead of doing that, every test case in ShiftRotTestCase puts some
  76 # data into the test_data list below, describing the instructions to
  77 # be tested and the initial state. Once all the tests have been run,
  78 # test_data gets passed to TestRunner which then sets up the DUT and
  79 # simulator once, runs all the data through it, and asserts that the
  80 # results match the pseudocode sim at every cycle.
  81
  82 # By doing this, I've reduced the time it takes to run the test suite
  83 # massively. Before, it took around 1 minute on my computer, now it
  84 # takes around 3 seconds
  85
  86 test_data = []
  87
  88
  89 class ShiftRotTestCase(FHDLTestCase):
  90     def __init__(self, name):
  91         super().__init__(name)
  92         self.test_name = name
  93     def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}):
  94         tc = TestCase(prog, initial_regs, initial_sprs, self.test_name)
  95         test_data.append(tc)
  96
  97
  98     def test_shift(self):
  99         insns = ["slw", "sld", "srw", "srd", "sraw", "srad"]
 100         for i in range(20):
 101             choice = random.choice(insns)
 102             lst = [f"{choice} 3, 1, 2"]
 103             initial_regs = [0] * 32
 104             initial_regs[1] = random.randint(0, (1<<64)-1)
 105             initial_regs[2] = random.randint(0, 63)
 106             print(initial_regs[1], initial_regs[2])
 107             self.run_tst_program(Program(lst), initial_regs)
 108
 109
 110     def test_shift_arith(self):
 111         lst = ["sraw 3, 1, 2"]
 112         initial_regs = [0] * 32
 113         initial_regs[1] = random.randint(0, (1<<64)-1)
 114         initial_regs[2] = random.randint(0, 63)
 115         print(initial_regs[1], initial_regs[2])
 116         self.run_tst_program(Program(lst), initial_regs)
 117
 118     def test_shift_once(self):
 119         lst = ["slw 3, 1, 4",
 120                "slw 3, 1, 2"]
 121         initial_regs = [0] * 32
 122         initial_regs[1] = 0x80000000
 123         initial_regs[2] = 0x40
 124         initial_regs[4] = 0x00
 125         self.run_tst_program(Program(lst), initial_regs)
 126
 127     def test_rlwinm(self):
 128         for i in range(10):
 129             mb = random.randint(0,31)
 130             me = random.randint(0,31)
 131             sh = random.randint(0,31)
 132             lst = [f"rlwinm 3, 1, {mb}, {me}, {sh}"]
 133             initial_regs = [0] * 32
 134             initial_regs[1] = random.randint(0, (1<<64)-1)
 135             self.run_tst_program(Program(lst), initial_regs)
 136
 137     def test_rlwimi(self):
 138         lst = ["rlwimi 3, 1, 5, 20, 6"]
 139         initial_regs = [0] * 32
 140         initial_regs[1] = 0xdeadbeef
 141         initial_regs[3] = 0x12345678
 142         self.run_tst_program(Program(lst), initial_regs)
 143
 144     def test_rlwnm(self):
 145         lst = ["rlwnm 3, 1, 2, 20, 6"]
 146         initial_regs = [0] * 32
 147         initial_regs[1] = random.randint(0, (1<<64)-1)
 148         initial_regs[2] = random.randint(0, 63)
 149         self.run_tst_program(Program(lst), initial_regs)
 150
 151     def test_rldicl(self):
 152         lst = ["rldicl 3, 1, 5, 20"]
 153         initial_regs = [0] * 32
 154         initial_regs[1] = random.randint(0, (1<<64)-1)
 155         self.run_tst_program(Program(lst), initial_regs)
 156
 157     def test_rldicr(self):
 158         lst = ["rldicr 3, 1, 5, 20"]
 159         initial_regs = [0] * 32
 160         initial_regs[1] = random.randint(0, (1<<64)-1)
 161         self.run_tst_program(Program(lst), initial_regs)
 162
 163     def test_rlc(self):
 164         insns = ["rldic", "rldicl", "rldicr"]
 165         for i in range(20):
 166             choice = random.choice(insns)
 167             sh = random.randint(0, 63)
 168             m = random.randint(0, 63)
 169             lst = [f"{choice} 3, 1, {sh}, {m}"]
 170             initial_regs = [0] * 32
 171             initial_regs[1] = random.randint(0, (1<<64)-1)
 172             self.run_tst_program(Program(lst), initial_regs)
 173
 174     def test_ilang(self):
 175         pspec = ShiftRotPipeSpec(id_wid=2)
 176         alu = ShiftRotBasePipe(pspec)
 177         vl = rtlil.convert(alu, ports=alu.ports())
 178         with open("pipeline.il", "w") as f:
 179             f.write(vl)
 180
 181
 182 class TestRunner(FHDLTestCase):
 183     def __init__(self, test_data):
 184         super().__init__("run_all")
 185         self.test_data = test_data
 186
 187     def run_all(self):
 188         m = Module()
 189         comb = m.d.comb
 190         instruction = Signal(32)
 191
 192         pdecode = create_pdecode()
 193
 194         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 195
 196         pspec = ShiftRotPipeSpec(id_wid=2)
 197         m.submodules.alu = alu = ShiftRotBasePipe(pspec)
 198
 199         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 200         comb += alu.p.valid_i.eq(1)
 201         comb += alu.n.ready_i.eq(1)
 202         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 203         sim = Simulator(m)
 204
 205         sim.add_clock(1e-6)
 206         def process():
 207             for test in self.test_data:
 208                 print(test.name)
 209                 program = test.program
 210                 self.subTest(test.name)
 211                 simulator = ISA(pdecode2, test.regs, test.sprs, 0)
 212                 gen = program.generate_instructions()
 213                 instructions = list(zip(gen, program.assembly.splitlines()))
 214
 215                 index = simulator.pc.CIA.value//4
 216                 while index < len(instructions):
 217                     ins, code = instructions[index]
 218
 219                     print("0x{:X}".format(ins & 0xffffffff))
 220                     print(code)
 221
 222                     # ask the decoder to decode this binary data (endian'd)
 223                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 224                     yield instruction.eq(ins)          # raw binary instr.
 225                     yield Settle()
 226                     fn_unit = yield pdecode2.e.fn_unit
 227                     self.assertEqual(fn_unit, Function.SHIFT_ROT.value)
 228                     yield from set_alu_inputs(alu, pdecode2, simulator)
 229                     yield from set_extra_alu_inputs(alu, pdecode2, simulator)
 230                     yield
 231                     opname = code.split(' ')[0]
 232                     yield from simulator.call(opname)
 233                     index = simulator.pc.CIA.value//4
 234
 235                     vld = yield alu.n.valid_o
 236                     while not vld:
 237                         yield
 238                         vld = yield alu.n.valid_o
 239                     yield
 240                     alu_out = yield alu.n.data_o.o
 241                     out_reg_valid = yield pdecode2.e.write_reg.ok
 242                     if out_reg_valid:
 243                         write_reg_idx = yield pdecode2.e.write_reg.data
 244                         expected = simulator.gpr(write_reg_idx).value
 245                         msg = f"expected {expected:x}, actual: {alu_out:x}"
 246                         self.assertEqual(expected, alu_out, msg)
 247                     yield from self.check_extra_alu_outputs(alu, pdecode2,
 248                                                             simulator)
 249
 250         sim.add_sync_process(process)
 251         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
 252                             traces=[]):
 253             sim.run()
 254
 255     def check_extra_alu_outputs(self, alu, dec2, sim):
 256         rc = yield dec2.e.rc.data
 257         if rc:
 258             cr_expected = sim.crl[0].get_range().value
 259             cr_actual = yield alu.n.data_o.cr0
 260             self.assertEqual(cr_expected, cr_actual)
 261
 262
 263 if __name__ == "__main__":
 264     unittest.main(exit=False)
 265     suite = unittest.TestSuite()
 266     suite.addTest(TestRunner(test_data))
 267
 268     runner = unittest.TextTestRunner()
 269     runner.run(suite)