src/soc/fu/spr/main_stage.py

   1 """SPR Pipeline
   2
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=348
   4 * https://libre-soc.org/openpower/isa/sprset/
   5 """
   6
   7 from nmigen import (Module, Signal, Cat)
   8 from nmutil.pipemodbase import PipeModBase
   9 from soc.fu.spr.pipe_data import SPRInputData, SPROutputData
  10 from soc.decoder.power_enums import MicrOp, SPR, XER_bits
  11
  12 from soc.decoder.power_fields import DecodeFields
  13 from soc.decoder.power_fieldsn import SignalBitRange
  14 from soc.decoder.power_decoder2 import decode_spr_num
  15
  16
  17 class SPRMainStage(PipeModBase):
  18     def __init__(self, pspec):
  19         super().__init__(pspec, "spr_main")
  20         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
  21         self.fields.create_specs()
  22
  23     def ispec(self):
  24         return SPRInputData(self.pspec)
  25
  26     def ospec(self):
  27         return SPROutputData(self.pspec)
  28
  29     def elaborate(self, platform):
  30         m = Module()
  31         comb = m.d.comb
  32         op = self.i.ctx.op
  33
  34         # convenience variables
  35         a_i, spr1_i, fast1_i = self.i.a, self.i.spr1, self.i.fast1
  36         so_i, ov_i, ca_i = self.i.xer_so, self.i.xer_ov, self.i.xer_ca
  37         so_o, ov_o, ca_o = self.o.xer_so, self.o.xer_ov, self.o.xer_ca
  38         o, spr1_o, fast1_o = self.o.o, self.o.spr1, self.o.fast1
  39
  40         # take copy of D-Form TO field
  41         x_fields = self.fields.FormXFX
  42         spr = Signal(len(x_fields.SPR))
  43         comb += spr.eq(decode_spr_num(x_fields.SPR))
  44
  45         # TODO: some #defines for the bits n stuff.
  46         with m.Switch(op.insn_type):
  47             #### MTSPR ####
  48             with m.Case(MicrOp.OP_MTSPR):
  49                 with m.Switch(spr):
  50                     # fast SPRs first
  51                     with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0,
  52                                 SPR.SRR1, SPR.XER, SPR.DEC):
  53                         comb += fast1_o.data.eq(a_i)
  54                         comb += fast1_o.ok.eq(1)
  55                         # XER is constructed
  56                         with m.If(spr == SPR.XER):
  57                             # sticky
  58                             comb += so_o.data.eq(a_i[63-XER_bits['SO']])
  59                             comb += so_o.ok.eq(1)
  60                             # overflow
  61                             comb += ov_o.data[0].eq(a_i[63-XER_bits['OV']])
  62                             comb += ov_o.data[1].eq(a_i[63-XER_bits['OV32']])
  63                             comb += ov_o.ok.eq(1)
  64                             # carry
  65                             comb += ca_o.data[0].eq(a_i[63-XER_bits['CA']])
  66                             comb += ca_o.data[1].eq(a_i[63-XER_bits['CA32']])
  67                             comb += ca_o.ok.eq(1)
  68
  69                     # slow SPRs TODO
  70
  71             # move from SPRs
  72             with m.Case(MicrOp.OP_MFSPR):
  73                 comb += o.ok.eq(1)
  74                 with m.Switch(spr):
  75                     # fast SPRs first
  76                     with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0, SPR.SRR1,
  77                                 SPR.XER, SPR.DEC, SPR.TB):
  78                         comb += o.data.eq(fast1_i)
  79                         with m.If(spr == SPR.XER):
  80                             # bits 0:31 and 35:43 are treated as reserved
  81                             # and return 0s when read using mfxer
  82                             comb += o[32:64].eq(0)       # MBS0 bits 0-31
  83                             comb += o[63-43:64-35].eq(0) # MSB0 bits 35-43
  84                             # sticky
  85                             comb += o[63-XER_bits['SO']].eq(so_i)
  86                             # overflow
  87                             comb += o[63-XER_bits['OV']].eq(ov_i[0])
  88                             comb += o[63-XER_bits['OV32']].eq(ov_i[1])
  89                             # carry
  90                             comb += o[63-XER_bits['CA']].eq(ca_i[0])
  91                             comb += o[63-XER_bits['CA32']].eq(ca_i[1])
  92                     with m.Case(SPR.TBU):
  93                         comb += o.data[0:32].eq(fast1_i[32:64])
  94
  95                     # slow SPRs TODO
  96
  97         comb += self.o.ctx.eq(self.i.ctx)
  98
  99         return m