src/soc/fu/trap/pipe_data.py

   1 from nmigen import Signal, Const
   2 from ieee754.fpcommon.getop import FPPipeContext
   3 from soc.fu.alu.pipe_data import IntegerData
   4 from soc.decoder.power_decoder2 import Data
   5
   6
   7 class TrapInputData(IntegerData):
   8     regspec = [('INT', 'a', '0:63'),
   9                ('INT', 'b', '0:63'),
  10                ('PC', 'cia', '0:63'),
  11                ('MSR', 'msr', '0:63')]
  12     def __init__(self, pspec):
  13         super().__init__(pspec)
  14         self.a = Signal(64, reset_less=True)  # RA
  15         self.b = Signal(64, reset_less=True)  # RB/immediate
  16         self.cia = Signal(64, reset_less=True)  # Program counter
  17         self.msr = Signal(64, reset_less=True)  # MSR
  18
  19     def __iter__(self):
  20         yield from super().__iter__()
  21         yield self.a
  22         yield self.b
  23         yield self.cia
  24         yield self.msr
  25
  26     def eq(self, i):
  27         lst = super().eq(i)
  28         return lst + [self.a.eq(i.a), self.b.eq(i.b),
  29                       self.cia.eq(i.nia), self.msr.eq(i.msr)]
  30
  31
  32 class TrapOutputData(IntegerData):
  33     regspec = [('SPR', 'srr0', '0:63'),
  34                ('SPR', 'srr1', '0:63'),
  35                ('PC', 'nia', '0:63'),
  36                ('MSR', 'msr', '0:63')]
  37     def __init__(self, pspec):
  38         super().__init__(pspec)
  39         self.srr0 = Data(64, name="srr0") # SRR0 SPR
  40         self.srr1 = Data(64, name="srr1") # SRR1 SPR
  41         self.nia = Data(64, name="nia") # NIA (Next PC)
  42         self.msr = Signal(64, reset_less=True) # MSR
  43
  44     def __iter__(self):
  45         yield from super().__iter__()
  46         yield self.nia
  47         yield self.msr
  48         yield self.srr0
  49         yield self.srr1
  50
  51     def eq(self, i):
  52         lst = super().eq(i)
  53         return lst + [ self.nia.eq(i.nia), self.msr.eq(i.msr),
  54                       self.srr0.eq(i.srr0), self.srr1.eq(i.srr1)]