1 from soc
.fu
.pipe_data
import FUBaseData
, CommonPipeSpec
2 from soc
.fu
.trap
.trap_input_record
import CompTrapOpSubset
5 class TrapInputData(FUBaseData
):
6 regspec
= [('INT', 'ra', '0:63'), # RA
7 ('INT', 'rb', '0:63'), # RB/immediate
8 ('FAST', 'fast1', '0:63'), # SRR0
9 ('FAST', 'fast2', '0:63'), # SRR1
10 ('FAST', 'fast3', '0:63'), # SVSRR0
11 # note here that neither MSR nor CIA are read as regs: they are
12 # passed in as incoming "State", via the CompTrapOpSubset
14 def __init__(self
, pspec
):
15 super().__init
__(pspec
, False)
17 self
.srr0
, self
.srr1
, self
.svsrr0
= self
.fast1
, self
.fast2
, self
.fast3
18 self
.a
, self
.b
= self
.ra
, self
.rb
21 class TrapOutputData(FUBaseData
):
22 regspec
= [('INT', 'o', '0:63'), # RA
23 ('FAST', 'fast1', '0:63'), # SRR0 SPR
24 ('FAST', 'fast2', '0:63'), # SRR1 SPR
25 ('FAST', 'fast3', '0:63'), # SRR2 SPR
26 ('STATE', 'nia', '0:63'), # NIA (Next PC)
27 ('STATE', 'msr', '0:63')] # MSR
28 def __init__(self
, pspec
):
29 super().__init
__(pspec
, True)
31 self
.srr0
, self
.srr1
, self
.svsrr0
= self
.fast1
, self
.fast2
, self
.fast3
35 class TrapPipeSpec(CommonPipeSpec
):
36 regspec
= (TrapInputData
.regspec
, TrapOutputData
.regspec
)
37 opsubsetkls
= CompTrapOpSubset