src/soc/fu/trap/pipe_data.py

   1 from nmigen import Signal, Const
   2 from ieee754.fpcommon.getop import FPPipeContext
   3 from soc.fu.pipe_data import IntegerData
   4 from soc.decoder.power_decoder2 import Data
   5 from nmutil.dynamicpipe import SimpleHandshakeRedir
   6 from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
   7
   8
   9 class TrapInputData(IntegerData):
  10     regspec = [('INT', 'a', '0:63'),
  11                ('INT', 'b', '0:63'),
  12                ('PC', 'cia', '0:63'),
  13                ('MSR', 'msr', '0:63')]
  14     def __init__(self, pspec):
  15         super().__init__(pspec)
  16         self.a = Signal(64, reset_less=True)  # RA
  17         self.b = Signal(64, reset_less=True)  # RB/immediate
  18         self.cia = Signal(64, reset_less=True)  # Program counter
  19         self.msr = Signal(64, reset_less=True)  # MSR
  20
  21     def __iter__(self):
  22         yield from super().__iter__()
  23         yield self.a
  24         yield self.b
  25         yield self.cia
  26         yield self.msr
  27
  28     def eq(self, i):
  29         lst = super().eq(i)
  30         return lst + [self.a.eq(i.a), self.b.eq(i.b),
  31                       self.cia.eq(i.nia), self.msr.eq(i.msr)]
  32
  33
  34 class TrapOutputData(IntegerData):
  35     regspec = [('INT', 'o', '0:63'),
  36                ('SPR', 'srr0', '0:63'),
  37                ('SPR', 'srr1', '0:63'),
  38                ('PC', 'nia', '0:63'),
  39                ('MSR', 'msr', '0:63')]
  40     def __init__(self, pspec):
  41         super().__init__(pspec)
  42         self.o = Data(64, name="o")       # RA
  43         self.srr0 = Data(64, name="srr0") # SRR0 SPR
  44         self.srr1 = Data(64, name="srr1") # SRR1 SPR
  45         self.nia = Data(64, name="nia") # NIA (Next PC)
  46         self.msr = Data(64, name="msr") # MSR
  47
  48     def __iter__(self):
  49         yield from super().__iter__()
  50         yield self.o
  51         yield self.nia
  52         yield self.msr
  53         yield self.srr0
  54         yield self.srr1
  55
  56     def eq(self, i):
  57         lst = super().eq(i)
  58         return lst + [ self.o.eq(i.o), self.nia.eq(i.nia), self.msr.eq(i.msr),
  59                       self.srr0.eq(i.srr0), self.srr1.eq(i.srr1)]
  60
  61
  62 # TODO: replace CompALUOpSubset with CompTrapOpSubset
  63 class TrapPipeSpec:
  64     regspec = (TrapInputData.regspec, TrapOutputData.regspec)
  65     opsubsetkls = CompALUOpSubset
  66     def __init__(self, id_wid, op_wid):
  67         self.id_wid = id_wid
  68         self.op_wid = op_wid
  69         self.opkls = lambda _: self.opsubsetkls(name="op")
  70         self.stage = None
  71         self.pipekls = SimpleHandshakeRedir