src/soc/litex/florent/Makefile

   1 ls180:
   2         ./ls180soc.py --build --platform=ls180
   3         cp build/ls180/gateware/ls180.v .
   4         cp build/ls180/gateware/mem.init .
   5         cp libresoc/libresoc.v .
   6         yosys -p 'read_verilog ls180.v; read_verilog libresoc.v; write_ilang ls180.il'
   7         yosys -p 'read_verilog ls180.v' \
   8           -p 'read_verilog libresoc.v' \
   9           -p 'write_ilang ls180.il'