src/soc/litex/florent/libresoc/core.py

   1 import os
   2
   3 from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
   4
   5 from litex.soc.interconnect import wishbone as wb
   6 from litex.soc.cores.cpu import CPU
   7
   8 from soc.config.pinouts import get_pinspecs
   9 from soc.debug.jtag import Pins
  10 from c4m.nmigen.jtag.tap import IOType
  11
  12 from libresoc.ls180 import io
  13 from litex.build.generic_platform import ConstraintManager
  14
  15
  16 CPU_VARIANTS = ["standard", "standard32", "standardjtag",
  17                 "standardjtagtestgpio", "ls180",
  18                 "standardjtagnoirq"]
  19
  20
  21 def make_wb_bus(prefix, obj, simple=False):
  22     res = {}
  23     outpins = ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']
  24     if not simple:
  25         outpins += ['cti', 'bte']
  26     for o in outpins:
  27         res['o_%s__%s' % (prefix, o)] = getattr(obj, o)
  28     for i in ['ack', 'err', 'dat_r']:
  29         res['i_%s__%s' % (prefix, i)] = getattr(obj, i)
  30     return res
  31
  32 def make_wb_slave(prefix, obj):
  33     res = {}
  34     for i in ['stb', 'cyc', 'cti', 'bte', 'we', 'adr', 'dat_w', 'sel']:
  35         res['i_%s__%s' % (prefix, i)] = getattr(obj, i)
  36     for o in ['ack', 'err', 'dat_r']:
  37         res['o_%s__%s' % (prefix, o)] = getattr(obj, o)
  38     return res
  39
  40 def make_pad(res, dirn, name, suffix, cpup, iop):
  41     cpud, iod = ('i', 'o') if dirn else ('o', 'i')
  42     cname = '%s_%s__core__%s' % (cpud, name, suffix)
  43     pname = '%s_%s__pad__%s' % (iod, name, suffix)
  44     print ("make pad", name, dirn, cpud, iod, cname, pname, suffix, cpup, iop)
  45     res[cname], res[pname] = cpup, iop
  46
  47 def get_field(rec, name):
  48     for f in rec.layout:
  49         f = f[0]
  50         if f.endswith(name):
  51             return getattr(rec, f)
  52
  53
  54 def make_jtag_ioconn(res, pin, cpupads, iopads):
  55     (fn, pin, iotype, pin_name, scan_idx) = pin
  56     #serial_tx__core__o, serial_rx__pad__i,
  57     # special-case sdram_clock
  58     if pin == 'clock' and fn == 'sdr':
  59         cpu = cpupads['sdram_clock']
  60         io = iopads['sdram_clock']
  61     else:
  62         cpu = cpupads[fn]
  63         io = iopads[fn]
  64     print ("cpupads", cpupads)
  65     print ("iopads", iopads)
  66     print ("pin", fn, pin, iotype, pin_name)
  67     print ("cpu fn", cpu)
  68     print ("io fn", io)
  69     name = "%s_%s" % (fn, pin)
  70     print ("name", name)
  71     sigs = []
  72
  73     if iotype in (IOType.In, IOType.Out):
  74         ps = pin.split("_")
  75         if pin == 'clock' and fn == 'sdr':
  76             cpup = cpu
  77             iop = io
  78         elif len(ps) == 2 and ps[-1].isdigit():
  79             pin, idx = ps
  80             idx = int(idx)
  81             print ("ps split", pin, idx)
  82             cpup = getattr(cpu, pin)[idx]
  83             iop = getattr(io, pin)[idx]
  84         elif pin.isdigit():
  85             idx = int(pin)
  86             print ("digit", idx)
  87             cpup = cpu[idx]
  88             iop = io[idx]
  89         else:
  90             cpup = getattr(cpu, pin)
  91             iop = getattr(io, pin)
  92
  93     if iotype == IOType.Out:
  94         # output from the pad is routed through C4M JTAG and so
  95         # is an *INPUT* into core.  ls180soc connects this to "real" peripheral
  96         make_pad(res, True, name, "o", cpup, iop)
  97
  98     elif iotype == IOType.In:
  99         # input to the pad is routed through C4M JTAG and so
 100         # is an *OUTPUT* into core.  ls180soc connects this to "real" peripheral
 101         make_pad(res, True, name, "i", cpup, iop)
 102
 103     elif iotype == IOType.InTriOut:
 104         if fn == 'gpio': # sigh decode GPIO special-case
 105             idx = int(pin[1:])
 106             oe_idx = idx
 107         elif fn == 'sdr': # sigh
 108             idx = int(pin.split('_')[-1])
 109             oe_idx = 0
 110         else:
 111             idx = 0
 112             oe_idx = 0
 113         print ("gpio tri", fn, pin, iotype, pin_name, scan_idx, idx)
 114         cpup, iop = get_field(cpu, "i")[idx], get_field(io, "i")[idx]
 115         make_pad(res, True, name, "i", cpup, iop)
 116         cpup, iop = get_field(cpu, "o")[idx], get_field(io, "o")[idx]
 117         make_pad(res, True, name, "o", cpup, iop)
 118         cpup, iop = get_field(cpu, "oe")[oe_idx], get_field(io, "oe")[oe_idx]
 119         make_pad(res, True, name, "oe", cpup, iop)
 120
 121     if iotype in (IOType.In, IOType.InTriOut):
 122         sigs.append(("i", 1))
 123     if iotype in (IOType.Out, IOType.TriOut, IOType.InTriOut):
 124         sigs.append(("o", 1))
 125     if iotype in (IOType.TriOut, IOType.InTriOut):
 126         sigs.append(("oe", 1))
 127
 128
 129 class LibreSoC(CPU):
 130     name                 = "libre_soc"
 131     human_name           = "Libre-SoC"
 132     variants             = CPU_VARIANTS
 133     endianness           = "little"
 134     gcc_triple           = ("powerpc64le-linux", "powerpc64le-linux-gnu")
 135     linker_output_format = "elf64-powerpcle"
 136     nop                  = "nop"
 137     io_regions           = {0xc0000000: 0x10000000} # origin, length
 138
 139     @property
 140     def mem_map(self):
 141         return {"csr": 0xc0000000}
 142
 143     @property
 144     def gcc_flags(self):
 145         flags  = "-m64 "
 146         flags += "-mabi=elfv2 "
 147         flags += "-msoft-float "
 148         flags += "-mno-string "
 149         flags += "-mno-multiple "
 150         flags += "-mno-vsx "
 151         flags += "-mno-altivec "
 152         flags += "-mlittle-endian "
 153         flags += "-mstrict-align "
 154         flags += "-fno-stack-protector "
 155         flags += "-mcmodel=small "
 156         flags += "-D__microwatt__ "
 157         return flags
 158
 159     def __init__(self, platform, variant="standard"):
 160         self.platform     = platform
 161         self.variant      = variant
 162         self.reset        = Signal()
 163
 164         irq_en = "noirq" not in variant
 165
 166         if irq_en:
 167             self.interrupt    = Signal(16)
 168
 169         if variant == "standard32":
 170             self.data_width           = 32
 171             self.dbus = dbus = wb.Interface(data_width=32, adr_width=30)
 172         else:
 173             self.dbus = dbus = wb.Interface(data_width=64, adr_width=29)
 174             self.data_width           = 64
 175         self.ibus = ibus = wb.Interface(data_width=64, adr_width=29)
 176
 177         self.xics_icp = icp = wb.Interface(data_width=32, adr_width=30)
 178         self.xics_ics = ics = wb.Interface(data_width=32, adr_width=30)
 179
 180         jtag_en = ('jtag' in variant) or variant == 'ls180'
 181
 182         if "testgpio" in variant:
 183             self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
 184         if jtag_en:
 185             self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
 186
 187         self.periph_buses = [ibus, dbus]
 188         self.memory_buses = []
 189
 190         if jtag_en:
 191             self.periph_buses.append(jtag_wb)
 192             self.jtag_tck = Signal(1)
 193             self.jtag_tms = Signal(1)
 194             self.jtag_tdi = Signal(1)
 195             self.jtag_tdo = Signal(1)
 196         else:
 197             self.dmi_addr = Signal(4)
 198             self.dmi_din = Signal(64)
 199             self.dmi_dout = Signal(64)
 200             self.dmi_wr = Signal(1)
 201             self.dmi_ack = Signal(1)
 202             self.dmi_req = Signal(1)
 203
 204         # # #
 205
 206         self.cpu_params = dict(
 207             # Clock / Reset
 208             i_clk              = ClockSignal(),
 209             i_rst              = ResetSignal() | self.reset,
 210
 211             # Monitoring / Debugging
 212             i_pc_i             = 0,
 213             i_pc_i_ok          = 0,
 214             i_core_bigendian_i = 0, # Signal(),
 215             o_busy_o           = Signal(),   # not connected
 216             o_memerr_o         = Signal(),   # not connected
 217             o_pc_o             = Signal(64), # not connected
 218         )
 219
 220         if irq_en:
 221             # interrupts
 222             self.cpu_params['i_int_level_i'] = self.interrupt
 223
 224         if jtag_en:
 225             self.cpu_params.update(dict(
 226                 # JTAG Debug bus
 227                 o_TAP_bus__tdo = self.jtag_tdo,
 228                 i_TAP_bus__tdi = self.jtag_tdi,
 229                 i_TAP_bus__tms = self.jtag_tms,
 230                 i_TAP_bus__tck = self.jtag_tck,
 231             ))
 232         else:
 233             self.cpu_params.update(dict(
 234                 # DMI Debug bus
 235                 i_dmi_addr_i          = self.dmi_addr,
 236                 i_dmi_din             = self.dmi_din,
 237                 o_dmi_dout            = self.dmi_dout,
 238                 i_dmi_req_i           = self.dmi_req,
 239                 i_dmi_we_i            = self.dmi_wr,
 240                 o_dmi_ack_o           = self.dmi_ack,
 241             ))
 242
 243         # add clock select, pll output
 244         if variant == "ls180":
 245             self.pll_18_o = Signal()
 246             self.clk_sel = Signal(2)
 247             self.pll_lck_o = Signal()
 248             self.cpu_params['i_clk_sel_i'] = self.clk_sel
 249             self.cpu_params['o_pll_18_o'] = self.pll_18_o
 250             self.cpu_params['o_pll_lck_o'] = self.pll_lck_o
 251
 252         # add wishbone buses to cpu params
 253         self.cpu_params.update(make_wb_bus("ibus", ibus))
 254         self.cpu_params.update(make_wb_bus("dbus", dbus))
 255         self.cpu_params.update(make_wb_slave("ics_wb", ics))
 256         self.cpu_params.update(make_wb_slave("icp_wb", icp))
 257         if "testgpio" in variant:
 258             self.cpu_params.update(make_wb_slave("gpio_wb", gpio))
 259         if jtag_en:
 260             self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))
 261
 262         if variant == 'ls180':
 263             # urr yuk.  have to expose iopads / pins from core to litex
 264             # then back again.  cut _some_ of that out by connecting
 265             self.padresources = io()
 266             self.pad_cm = ConstraintManager(self.padresources, [])
 267             self.cpupads = {}
 268             iopads = {}
 269             litexmap = {}
 270             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
 271                       'pwm', 'sd0', 'sdr'}
 272             for periph in subset:
 273                 origperiph = periph
 274                 num = None
 275                 if periph[-1].isdigit():
 276                     periph, num = periph[:-1], int(periph[-1])
 277                 print ("periph request", periph, num)
 278                 if periph == 'mspi':
 279                     if num == 0:
 280                         periph, num = 'spimaster', None
 281                     else:
 282                         periph, num = 'spisdcard', None
 283                 elif periph == 'sdr':
 284                     periph = 'sdram'
 285                 elif periph == 'mtwi':
 286                     periph = 'i2c'
 287                 elif periph == 'sd':
 288                     periph, num = 'sdcard', None
 289                 litexmap[origperiph] = (periph, num)
 290                 self.cpupads[origperiph] = platform.request(periph, num)
 291                 iopads[origperiph] = self.pad_cm.request(periph, num)
 292                 if periph == 'sdram':
 293                     # special-case sdram clock
 294                     ck = platform.request("sdram_clock")
 295                     self.cpupads['sdram_clock'] = ck
 296                     ck = self.pad_cm.request("sdram_clock")
 297                     iopads['sdram_clock'] = ck
 298
 299             pinset = get_pinspecs(subset=subset)
 300             p = Pins(pinset)
 301             for pin in list(p):
 302                 make_jtag_ioconn(self.cpu_params, pin, self.cpupads, iopads)
 303
 304         # add verilog sources
 305         self.add_sources(platform)
 306
 307     def set_reset_address(self, reset_address):
 308         assert not hasattr(self, "reset_address")
 309         self.reset_address = reset_address
 310         assert reset_address == 0x00000000
 311
 312     @staticmethod
 313     def add_sources(platform):
 314         cdir = os.path.dirname(__file__)
 315         platform.add_source(os.path.join(cdir, "libresoc.v"))
 316
 317     def do_finalize(self):
 318         self.specials += Instance("test_issuer", **self.cpu_params)
 319