src/soc/litex/florent/libresoc/ls180.py

   1 #
   2 # This file is part of LiteX.
   3 #
   4 # Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   5 # SPDX-License-Identifier: BSD-2-Clause
   6
   7 from migen.fhdl.structure import _Fragment
   8 from litex.build.generic_platform import (GenericPlatform, Pins,
   9                                         Subsignal, IOStandard, Misc,
  10                                         )
  11 import os
  12
  13 # IOs ----------------------------------------------------------------------------------------------
  14
  15 _io = [
  16     ("sys_clk", 0, Pins("G2"), IOStandard("LVCMOS33")),
  17     ("rst",   0, Pins("R1"), IOStandard("LVCMOS33")),
  18
  19     ("serial", 0,
  20         Subsignal("tx", Pins("L4"), IOStandard("LVCMOS33")),
  21         Subsignal("rx", Pins("M1"), IOStandard("LVCMOS33"))
  22     ),
  23
  24     ("serial", 1,
  25         Subsignal("tx", Pins("L4"), IOStandard("LVCMOS33")),
  26         Subsignal("rx", Pins("M1"), IOStandard("LVCMOS33"))
  27     ),
  28
  29     ("spi", 0,
  30         Subsignal("clk",  Pins("J1")),
  31         Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
  32         Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
  33         Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
  34         Misc("SLEWRATE=FAST"),
  35         IOStandard("LVCMOS33"),
  36     ),
  37
  38     ("spisdcard", 0,
  39         Subsignal("clk",  Pins("J1")),
  40         Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
  41         Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
  42         Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
  43         Misc("SLEWRATE=FAST"),
  44         IOStandard("LVCMOS33"),
  45     ),
  46
  47     ("sdcard", 0,
  48         Subsignal("clk",  Pins("J1")),
  49         Subsignal("cmd",  Pins("J3"), Misc("PULLMODE=UP")),
  50         Subsignal("data", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
  51         Misc("SLEWRATE=FAST"),
  52         IOStandard("LVCMOS33"),
  53     ),
  54
  55     ("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")),
  56     ("sdram", 0,
  57         Subsignal("a",     Pins(
  58             "M20 M19 L20 L19 K20 K19 K18 J20",
  59             "J19 H20 N19 G20 G19")),
  60         Subsignal("dq",    Pins(
  61             "J16 L18 M18 N18 P18 T18 T17 U20",
  62             "E19 D20 D19 C20 E18 F18 J18 J17")),
  63         Subsignal("we_n",  Pins("T20")),
  64         Subsignal("ras_n", Pins("R20")),
  65         Subsignal("cas_n", Pins("T19")),
  66         Subsignal("cs_n",  Pins("P20")),
  67         Subsignal("cke",   Pins("F20")),
  68         Subsignal("ba",    Pins("P19 N20")),
  69         Subsignal("dm",    Pins("U19 E20")),
  70         IOStandard("LVCMOS33"),
  71         Misc("SLEWRATE=FAST"),
  72     ),
  73
  74 ]
  75
  76 for i in range(8):
  77     _io.append( ("gpio_in", i, Pins("X%d" % i), IOStandard("LVCMOS33")) )
  78     _io.append( ("gpio_out", i, Pins("Y%d" % i), IOStandard("LVCMOS33")) )
  79
  80 # Platform -----------------------------------------------------------------------------------------
  81
  82 class LS180Platform(GenericPlatform):
  83     default_clk_name   = "sys_clk"
  84     default_clk_period = 1e9/50e6
  85
  86     def __init__(self, device="LS180", **kwargs):
  87         assert device in ["LS180"]
  88         GenericPlatform.__init__(self, device, _io, **kwargs)
  89
  90     def build(self, fragment,
  91                     build_dir      = "build",
  92                     build_name     = "top",
  93                     run            = True,
  94                     timingstrict   = True,
  95                     **kwargs):
  96
  97         platform = self
  98
  99         # Create build directory
 100         os.makedirs(build_dir, exist_ok=True)
 101         cwd = os.getcwd()
 102         os.chdir(build_dir)
 103
 104         # Finalize design
 105         if not isinstance(fragment, _Fragment):
 106             fragment = fragment.get_fragment()
 107         platform.finalize(fragment)
 108
 109         # Generate verilog
 110         v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
 111         named_sc, named_pc = platform.resolve_signals(v_output.ns)
 112         v_file = build_name + ".v"
 113         v_output.write(v_file)
 114         platform.add_source(v_file)
 115
 116         os.chdir(cwd)
 117
 118         return v_output.ns
 119
 120     def do_finalize(self, fragment):
 121         super().do_finalize(fragment)
 122         return
 123         self.add_period_constraint(self.lookup_request("clk", loose=True),
 124                                    1e9/50e6)