2 # This file is part of LiteX.
4 # Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
5 # SPDX-License-Identifier: BSD-2-Clause
7 from litex
.build
.generic_platform
import *
8 from litex
.build
.lattice
import LatticePlatform
9 from litex
.build
.lattice
.programmer
import UJProg
11 # IOs ----------------------------------------------------------------------------------------------
14 ("clk25", 0, Pins("G2"), IOStandard("LVCMOS33")),
15 ("rst", 0, Pins("R1"), IOStandard("LVCMOS33")),
17 ("user_led", 0, Pins("B2"), IOStandard("LVCMOS33")),
18 ("user_led", 1, Pins("C2"), IOStandard("LVCMOS33")),
19 ("user_led", 2, Pins("C1"), IOStandard("LVCMOS33")),
20 ("user_led", 3, Pins("D2"), IOStandard("LVCMOS33")),
21 ("user_led", 4, Pins("D1"), IOStandard("LVCMOS33")),
22 ("user_led", 5, Pins("E2"), IOStandard("LVCMOS33")),
23 ("user_led", 6, Pins("E1"), IOStandard("LVCMOS33")),
24 ("user_led", 7, Pins("H3"), IOStandard("LVCMOS33")),
27 Subsignal("tx", Pins("L4"), IOStandard("LVCMOS33")),
28 Subsignal("rx", Pins("M1"), IOStandard("LVCMOS33"))
32 Subsignal("clk", Pins("J1")),
33 Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
34 Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
35 Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
36 Misc("SLEWRATE=FAST"),
37 IOStandard("LVCMOS33"),
41 Subsignal("clk", Pins("J1")),
42 Subsignal("cmd", Pins("J3"), Misc("PULLMODE=UP")),
43 Subsignal("data", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
44 Misc("SLEWRATE=FAST"),
45 IOStandard("LVCMOS33"),
48 ("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")),
51 "M20 M19 L20 L19 K20 K19 K18 J20",
52 "J19 H20 N19 G20 G19")),
54 "J16 L18 M18 N18 P18 T18 T17 U20",
55 "E19 D20 D19 C20 E18 F18 J18 J17")),
56 Subsignal("we_n", Pins("T20")),
57 Subsignal("ras_n", Pins("R20")),
58 Subsignal("cas_n", Pins("T19")),
59 Subsignal("cs_n", Pins("P20")),
60 Subsignal("cke", Pins("F20")),
61 Subsignal("ba", Pins("P19 N20")),
62 Subsignal("dm", Pins("U19 E20")),
63 IOStandard("LVCMOS33"),
64 Misc("SLEWRATE=FAST"),
67 ("wifi_gpio0", 0, Pins("L2"), IOStandard("LVCMOS33")),
69 ("ext0p", 0, Pins("B11"), IOStandard("LVCMOS33")),
70 ("ext1p", 0, Pins("A10"), IOStandard("LVCMOS33")),
73 Subsignal("p", Pins("B11")),
74 Subsignal("n", Pins("C11")),
75 IOStandard("LVCMOS33")
78 Subsignal("p", Pins("A10")),
79 Subsignal("n", Pins("A11")),
80 IOStandard("LVCMOS33")
83 Subsignal("p", Pins("A9")),
84 Subsignal("n", Pins("B10")),
85 IOStandard("LVCMOS33")
88 Subsignal("p", Pins("B9")),
89 Subsignal("n", Pins("C10")),
90 IOStandard("LVCMOS33")
94 Subsignal("d_p", Pins("D15")),
95 Subsignal("d_n", Pins("E15")),
96 Subsignal("pullup", Pins("B12 C12")),
97 IOStandard("LVCMOS33")
100 Subsignal("clk", Pins("P4")),
101 Subsignal("mosi", Pins("P3")),
102 IOStandard("LVCMOS33"),
105 Subsignal("dc", Pins("P1")),
106 Subsignal("resn", Pins("P2")),
107 Subsignal("csn", Pins("N2")),
108 IOStandard("LVCMOS33"),
112 # Platform -----------------------------------------------------------------------------------------
114 class Platform(LatticePlatform
):
115 default_clk_name
= "clk25"
116 default_clk_period
= 1e9
/25e6
118 def __init__(self
, device
="LFE5U-45F", **kwargs
):
119 assert device
in ["LFE5U-25F", "LFE5U-45F", "LFE5U-85F"]
120 LatticePlatform
.__init
__(self
, device
+ "-6BG381C", _io
, **kwargs
)
122 def create_programmer(self
):
125 def do_finalize(self
, fragment
):
126 LatticePlatform
.do_finalize(self
, fragment
)
127 self
.add_period_constraint(self
.lookup_request("clk25", loose
=True), 1e9
/25e6
)