src/soc/litex/florent/sim.py

   1 #!/usr/bin/env python3
   2
   3 import os
   4 import argparse
   5
   6 from migen import (Signal, FSM, If, Display, Finish, NextValue, NextState)
   7
   8 from litex.build.generic_platform import Pins, Subsignal
   9 from litex.build.sim import SimPlatform
  10 from litex.build.io import CRG
  11 from litex.build.sim.config import SimConfig
  12
  13 from litex.soc.integration.soc import SoCRegion
  14 from litex.soc.integration.soc_core import SoCCore
  15 from litex.soc.integration.builder import Builder
  16
  17 from litex.tools.litex_sim import Platform
  18
  19 from libresoc import LibreSoC
  20 from microwatt import Microwatt
  21
  22 # LibreSoCSim -----------------------------------------------------------------
  23
  24 class LibreSoCSim(SoCCore):
  25     def __init__(self, cpu="libresoc", debug=False):
  26         assert cpu in ["libresoc", "microwatt"]
  27         platform     = Platform()
  28         sys_clk_freq = int(1e6)
  29
  30         # SoCCore -------------------------------------------------------------
  31         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
  32             cpu_type                 = "microwatt",
  33             cpu_cls                  = LibreSoC   if cpu == "libresoc" \
  34                                        else Microwatt,
  35             uart_name                = "sim",
  36             integrated_rom_size      = 0x10000,
  37             integrated_main_ram_size = 0x10000000) # 256MB
  38         self.platform.name = "sim"
  39
  40         # CRG -----------------------------------------------------------------
  41         self.submodules.crg = CRG(platform.request("sys_clk"))
  42
  43         # Debug ---------------------------------------------------------------
  44         if not debug:
  45             return
  46
  47         # setup running of DMI FSM
  48         dmi_addr = Signal(3)
  49         dmi_din = Signal(64)
  50         dmi_wen = Signal(64)
  51         dmi_dout = Signal(64)
  52         dmi_req = Signal(1)
  53
  54         uptime = Signal(64)
  55         # increment counter, Stop after 100000 cycles
  56         uptime = Signal(64)
  57         self.sync += uptime.eq(uptime + 1)
  58         self.sync += If(uptime == 100000, Finish())
  59
  60         dmifsm = FSM()
  61         self.submodules += dmifsm
  62
  63         # DMI FSM
  64         dmifsm.act("START",
  65             If(dmi_req & dmi_wen,
  66                 (self.cpu.dmi_addr.eq(dmi_addr),   # DMI Addr
  67                  self.cpu.dmi_din.eq(dmi_din), # DMI in
  68                  self.cpu.dmi_req.eq(1),    # DMI request
  69                  self.cpu.dmi_wr.eq(1),    # DMI write
  70                  If(self.cpu.dmi_ack,
  71                     (NextState("IDLE"),
  72                      self.cpu.dmi_addr.eq(0),
  73                      self.cpu.dmi_din.eq(0),
  74                      self.cpu.dmi_req.eq(0),
  75                      self.cpu.dmi_wr.eq(0),
  76                     )
  77                  ),
  78                 ),
  79             )
  80         )
  81
  82         dmifsm.act("IDLE",
  83             (NextValue(dmi_req, 0),
  84             )
  85         )
  86
  87         # kick off a "stop"
  88         self.comb += If(uptime == 0,
  89             (dmi_addr.eq(0), # CTRL
  90              dmi_din.eq(1<<0), # STOP
  91              dmi_req.eq(1),
  92              dmi_wen.eq(1),
  93             )
  94         )
  95
  96         # monitor ibus write
  97         self.sync += If(self.cpu.ibus.stb & self.cpu.ibus.ack &
  98                         self.cpu.ibus.we,
  99             Display("[%06x] iadr: %8x, s %01x w %016x",
 100                 uptime,
 101                 self.cpu.ibus.adr,
 102                 self.cpu.ibus.sel,
 103                 self.cpu.ibus.dat_w,
 104             )
 105         )
 106         # monitor ibus read
 107         self.sync += If(self.cpu.ibus.stb & self.cpu.ibus.ack &
 108                         ~self.cpu.ibus.we,
 109             Display("[%06x] iadr: %8x, s %01x r %016x",
 110                 uptime,
 111                 self.cpu.ibus.adr,
 112                 self.cpu.ibus.sel,
 113                 self.cpu.ibus.dat_r
 114             )
 115         )
 116
 117         # monitor bbus read/write
 118         self.sync += If(self.cpu.dbus.stb & self.cpu.dbus.ack,
 119             Display("[%06x] dadr: %8x, we %d s %01x w %016x r: %016x",
 120                 uptime,
 121                 self.cpu.dbus.adr,
 122                 self.cpu.dbus.we,
 123                 self.cpu.dbus.sel,
 124                 self.cpu.dbus.dat_w,
 125                 self.cpu.dbus.dat_r
 126             )
 127         )
 128
 129 # Build -----------------------------------------------------------------------
 130
 131 def main():
 132     parser = argparse.ArgumentParser(description="LiteX LibreSoC CPU Sim")
 133     parser.add_argument("--cpu",          default="libresoc",
 134                         help="CPU to use: libresoc (default) or microwatt")
 135     parser.add_argument("--debug",        action="store_true",
 136                         help="Enable debug traces")
 137     parser.add_argument("--trace",        action="store_true",
 138                         help="Enable tracing")
 139     parser.add_argument("--trace-start",  default=0,
 140                         help="Cycle to start FST tracing")
 141     parser.add_argument("--trace-end",    default=-1,
 142                         help="Cycle to end FST tracing")
 143     args = parser.parse_args()
 144
 145     sim_config = SimConfig(default_clk="sys_clk")
 146     sim_config.add_module("serial2console", "serial")
 147
 148     for i in range(2):
 149         soc = LibreSoCSim(cpu=args.cpu, debug=args.debug)
 150         builder = Builder(soc,compile_gateware = i!=0)
 151         builder.build(sim_config=sim_config,
 152             run         = i!=0,
 153             trace       = args.trace,
 154             trace_start = int(args.trace_start),
 155             trace_end   = int(args.trace_end),
 156             trace_fst   = 0)
 157         os.chdir("../")
 158
 159 if __name__ == "__main__":
 160     main()