src/soc/litex/florent/sim.py

   1 #!/usr/bin/env python3
   2
   3 import os
   4 import argparse
   5
   6 from migen import (Signal, FSM, If, Display, Finish, NextValue, NextState)
   7
   8 from litex.build.generic_platform import Pins, Subsignal
   9 from litex.build.sim import SimPlatform
  10 from litex.build.io import CRG
  11 from litex.build.sim.config import SimConfig
  12
  13 from litex.soc.integration.soc import SoCRegion
  14 from litex.soc.integration.soc_core import SoCCore
  15 from litex.soc.integration.soc_sdram import SoCSDRAM
  16 from litex.soc.integration.builder import Builder
  17 from litex.soc.integration.common import get_mem_data
  18
  19 from litedram import modules as litedram_modules
  20 from litedram.phy.model import SDRAMPHYModel
  21 from litex.tools.litex_sim import sdram_module_nphases, get_sdram_phy_settings
  22
  23 from litex.tools.litex_sim import Platform
  24
  25 from libresoc import LibreSoC
  26 from microwatt import Microwatt
  27
  28 # LibreSoCSim -----------------------------------------------------------------
  29
  30 class LibreSoCSim(SoCSDRAM):
  31     def __init__(self, cpu="libresoc", debug=False, with_sdram=True,
  32             sdram_module          = "AS4C16M16",
  33             #sdram_data_width      = 16,
  34             #sdram_module          = "MT48LC16M16",
  35             sdram_data_width      = 16,
  36             ):
  37         assert cpu in ["libresoc", "microwatt"]
  38         platform     = Platform()
  39         sys_clk_freq = int(100e6)
  40
  41         #cpu_data_width = 32
  42         cpu_data_width = 64
  43
  44         if cpu_data_width == 32:
  45             variant = "standard32"
  46         else:
  47             variant = "standard"
  48
  49         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
  50         #            "hello_world/hello_world.bin"
  51         ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
  52                     "tests/1.bin"
  53         #ram_fname = "/tmp/test.bin"
  54         #ram_fname = None
  55
  56         ram_init = []
  57         if ram_fname:
  58             #ram_init = get_mem_data({
  59             #    ram_fname:       "0x00000000",
  60             #    }, "little")
  61             ram_init = get_mem_data(ram_fname, "little")
  62
  63             # remap the main RAM to reset-start-address
  64             self.mem_map["main_ram"] = 0x00000000
  65
  66             # without sram nothing works, therefore move it to higher up
  67             self.mem_map["sram"] = 0x90000000
  68
  69
  70         # SoCCore -------------------------------------------------------------
  71         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
  72             cpu_type                 = "microwatt",
  73             cpu_cls                  = LibreSoC   if cpu == "libresoc" \
  74                                        else Microwatt,
  75             #bus_data_width           = 64,
  76             cpu_variant              = variant,
  77             csr_data_width            = 32,
  78             l2_size             = 0,
  79             uart_name                = "sim",
  80             with_sdram               = with_sdram,
  81             sdram_module          = sdram_module,
  82             sdram_data_width      = sdram_data_width,
  83             integrated_rom_size      = 0 if ram_fname else 0x10000,
  84             integrated_sram_size     = 0x40000,
  85             #integrated_main_ram_init  = ram_init,
  86             integrated_main_ram_size = 0x00000000 if with_sdram \
  87                                         else 0x10000000 , # 256MB
  88             )
  89         self.platform.name = "sim"
  90
  91         # CRG -----------------------------------------------------------------
  92         self.submodules.crg = CRG(platform.request("sys_clk"))
  93
  94         #ram_init = []
  95
  96         # SDRAM ----------------------------------------------------
  97         if with_sdram:
  98             sdram_clk_freq   = int(100e6) # FIXME: use 100MHz timings
  99             sdram_module_cls = getattr(litedram_modules, sdram_module)
 100             sdram_rate       = "1:{}".format(
 101                     sdram_module_nphases[sdram_module_cls.memtype])
 102             sdram_module     = sdram_module_cls(sdram_clk_freq, sdram_rate)
 103             phy_settings     = get_sdram_phy_settings(
 104                             memtype    = sdram_module.memtype,
 105                             data_width = sdram_data_width,
 106                             clk_freq   = sdram_clk_freq)
 107             self.submodules.sdrphy = SDRAMPHYModel(sdram_module,
 108                                                    phy_settings,
 109                                                    init=ram_init
 110                                                     )
 111             self.register_sdram(
 112                             self.sdrphy,
 113                             sdram_module.geom_settings,
 114                             sdram_module.timing_settings)
 115             # FIXME: skip memtest to avoid corrupting memory
 116             self.add_constant("MEMTEST_BUS_SIZE",  128//16)
 117             self.add_constant("MEMTEST_DATA_SIZE", 128//16)
 118             self.add_constant("MEMTEST_ADDR_SIZE", 128//16)
 119             self.add_constant("MEMTEST_BUS_DEBUG", 1)
 120             self.add_constant("MEMTEST_ADDR_DEBUG", 1)
 121             self.add_constant("MEMTEST_DATA_DEBUG", 1)
 122
 123
 124         # Debug ---------------------------------------------------------------
 125         if not debug:
 126             return
 127
 128         # setup running of DMI FSM
 129         dmi_addr = Signal(4)
 130         dmi_din = Signal(64)
 131         dmi_dout = Signal(64)
 132         dmi_wen = Signal(1)
 133         dmi_req = Signal(1)
 134
 135         # debug log out
 136         dbg_addr = Signal(4)
 137         dbg_dout = Signal(64)
 138         dbg_msg = Signal(1)
 139
 140         # capture pc from dmi
 141         pc = Signal(64)
 142         active_dbg = Signal()
 143         active_dbg_cr = Signal()
 144         active_dbg_xer = Signal()
 145
 146         # increment counter, Stop after 100000 cycles
 147         uptime = Signal(64)
 148         self.sync += uptime.eq(uptime + 1)
 149         #self.sync += If(uptime == 1000000000000, Finish())
 150
 151         # DMI FSM counter and FSM itself
 152         dmicount = Signal(10)
 153         dmirunning = Signal(1)
 154         dmi_monitor = Signal(1)
 155         dmifsm = FSM()
 156         self.submodules += dmifsm
 157
 158         # DMI FSM
 159         dmifsm.act("START",
 160             If(dmi_req & dmi_wen,
 161                 (self.cpu.dmi_addr.eq(dmi_addr),   # DMI Addr
 162                  self.cpu.dmi_din.eq(dmi_din), # DMI in
 163                  self.cpu.dmi_req.eq(1),    # DMI request
 164                  self.cpu.dmi_wr.eq(1),    # DMI write
 165                  If(self.cpu.dmi_ack,
 166                     (NextState("IDLE"),
 167                     )
 168                  ),
 169                 ),
 170             ),
 171             If(dmi_req & ~dmi_wen,
 172                 (self.cpu.dmi_addr.eq(dmi_addr),   # DMI Addr
 173                  self.cpu.dmi_req.eq(1),    # DMI request
 174                  self.cpu.dmi_wr.eq(0),    # DMI read
 175                  If(self.cpu.dmi_ack,
 176                     # acknowledge received: capture data.
 177                     (NextState("IDLE"),
 178                      NextValue(dbg_addr, dmi_addr),
 179                      NextValue(dbg_dout, self.cpu.dmi_dout),
 180                      NextValue(dbg_msg, 1),
 181                     ),
 182                  ),
 183                 ),
 184             )
 185         )
 186
 187         # DMI response received: reset the dmi request and check if
 188         # in "monitor" mode
 189         dmifsm.act("IDLE",
 190             If(dmi_monitor,
 191                  NextState("FIRE_MONITOR"), # fire "monitor" on next cycle
 192             ).Else(
 193                  NextState("START"), # back to start on next cycle
 194             ),
 195             NextValue(dmi_req, 0),
 196             NextValue(dmi_addr, 0),
 197             NextValue(dmi_din, 0),
 198             NextValue(dmi_wen, 0),
 199         )
 200
 201         # "monitor" mode fires off a STAT request
 202         dmifsm.act("FIRE_MONITOR",
 203             (NextValue(dmi_req, 1),
 204              NextValue(dmi_addr, 1), # DMI STAT address
 205              NextValue(dmi_din, 0),
 206              NextValue(dmi_wen, 0), # read STAT
 207              NextState("START"), # back to start on next cycle
 208             )
 209         )
 210
 211         # debug messages out
 212         self.sync += If(dbg_msg,
 213             (If(active_dbg & (dbg_addr == 0b10), # PC
 214                 Display("pc : %016x", dbg_dout),
 215              ),
 216              If(dbg_addr == 0b10, # PC
 217                  pc.eq(dbg_dout),     # capture PC
 218              ),
 219              #If(dbg_addr == 0b11, # MSR
 220              #   Display("    msr: %016x", dbg_dout),
 221              #),
 222              If(dbg_addr == 0b1000, # CR
 223                 Display("    cr : %016x", dbg_dout),
 224              ),
 225              If(dbg_addr == 0b1001, # XER
 226                 Display("    xer: %016x", dbg_dout),
 227              ),
 228              If(dbg_addr == 0b101, # GPR
 229                 Display("    gpr: %016x", dbg_dout),
 230              ),
 231             # also check if this is a "stat"
 232             If(dbg_addr == 1, # requested a STAT
 233                 #Display("    stat: %x", dbg_dout),
 234                 If(dbg_dout & 2, # bit 2 of STAT is "stopped" mode
 235                      dmirunning.eq(1), # continue running
 236                      dmi_monitor.eq(0), # and stop monitor mode
 237                 ),
 238             ),
 239              dbg_msg.eq(0)
 240             )
 241         )
 242
 243         # kick off a "stop"
 244         self.sync += If(uptime == 0,
 245             (dmi_addr.eq(0), # CTRL
 246              dmi_din.eq(1<<0), # STOP
 247              dmi_req.eq(1),
 248              dmi_wen.eq(1),
 249             )
 250         )
 251
 252         self.sync += If(uptime == 4,
 253              dmirunning.eq(1),
 254         )
 255
 256         self.sync += If(dmirunning,
 257              dmicount.eq(dmicount + 1),
 258         )
 259
 260         # loop every 1<<N cycles
 261         cyclewid = 9
 262
 263         # get the PC
 264         self.sync += If(dmicount == 4,
 265             (dmi_addr.eq(0b10), # NIA
 266              dmi_req.eq(1),
 267              dmi_wen.eq(0),
 268             )
 269         )
 270
 271         # kick off a "step"
 272         self.sync += If(dmicount == 8,
 273             (dmi_addr.eq(0), # CTRL
 274              dmi_din.eq(1<<3), # STEP
 275              dmi_req.eq(1),
 276              dmi_wen.eq(1),
 277              dmirunning.eq(0), # stop counter, need to fire "monitor"
 278              dmi_monitor.eq(1), # start "monitor" instead
 279             )
 280         )
 281
 282         # limit range of pc for debug reporting
 283         #self.comb += active_dbg.eq((0x378c <= pc) & (pc <= 0x38d8))
 284         #self.comb += active_dbg.eq((0x0 < pc) & (pc < 0x58))
 285         self.comb += active_dbg.eq(1)
 286
 287
 288         # get the MSR
 289         self.sync += If(active_dbg & (dmicount == 12),
 290             (dmi_addr.eq(0b11), # MSR
 291              dmi_req.eq(1),
 292              dmi_wen.eq(0),
 293             )
 294         )
 295
 296         if cpu == "libresoc":
 297             self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x1094c))
 298             #self.comb += active_dbg_cr.eq(1)
 299
 300             # get the CR
 301             self.sync += If(active_dbg_cr & (dmicount == 16),
 302                 (dmi_addr.eq(0b1000), # CR
 303                  dmi_req.eq(1),
 304                  dmi_wen.eq(0),
 305                 )
 306             )
 307
 308             #self.comb += active_dbg_xer.eq((0x10300 <= pc) & (pc <= 0x1094c))
 309             self.comb += active_dbg_xer.eq(active_dbg_cr)
 310
 311             # get the CR
 312             self.sync += If(active_dbg_xer & (dmicount == 20),
 313                 (dmi_addr.eq(0b1001), # XER
 314                  dmi_req.eq(1),
 315                  dmi_wen.eq(0),
 316                 )
 317             )
 318
 319         # read all 32 GPRs
 320         for i in range(32):
 321             self.sync += If(active_dbg & (dmicount == 24+(i*8)),
 322                 (dmi_addr.eq(0b100), # GSPR addr
 323                  dmi_din.eq(i), # r1
 324                  dmi_req.eq(1),
 325                  dmi_wen.eq(1),
 326                 )
 327             )
 328
 329             self.sync += If(active_dbg & (dmicount == 28+(i*8)),
 330                 (dmi_addr.eq(0b101), # GSPR data
 331                  dmi_req.eq(1),
 332                  dmi_wen.eq(0),
 333                 )
 334             )
 335
 336         # monitor bbus read/write
 337         self.sync += If(active_dbg & self.cpu.dbus.stb & self.cpu.dbus.ack,
 338             Display("    [%06x] dadr: %8x, we %d s %01x w %016x r: %016x",
 339                 #uptime,
 340                 0,
 341                 self.cpu.dbus.adr,
 342                 self.cpu.dbus.we,
 343                 self.cpu.dbus.sel,
 344                 self.cpu.dbus.dat_w,
 345                 self.cpu.dbus.dat_r
 346             )
 347         )
 348
 349         return
 350
 351         # monitor ibus write
 352         self.sync += If(active_dbg & self.cpu.ibus.stb & self.cpu.ibus.ack &
 353                         self.cpu.ibus.we,
 354             Display("    [%06x] iadr: %8x, s %01x w %016x",
 355                 #uptime,
 356                 0,
 357                 self.cpu.ibus.adr,
 358                 self.cpu.ibus.sel,
 359                 self.cpu.ibus.dat_w,
 360             )
 361         )
 362         # monitor ibus read
 363         self.sync += If(active_dbg & self.cpu.ibus.stb & self.cpu.ibus.ack &
 364                         ~self.cpu.ibus.we,
 365             Display("    [%06x] iadr: %8x, s %01x r %016x",
 366                 #uptime,
 367                 0,
 368                 self.cpu.ibus.adr,
 369                 self.cpu.ibus.sel,
 370                 self.cpu.ibus.dat_r
 371             )
 372         )
 373
 374 # Build -----------------------------------------------------------------------
 375
 376 def main():
 377     parser = argparse.ArgumentParser(description="LiteX LibreSoC CPU Sim")
 378     parser.add_argument("--cpu",          default="libresoc",
 379                         help="CPU to use: libresoc (default) or microwatt")
 380     parser.add_argument("--debug",        action="store_true",
 381                         help="Enable debug traces")
 382     parser.add_argument("--trace",        action="store_true",
 383                         help="Enable tracing")
 384     parser.add_argument("--trace-start",  default=0,
 385                         help="Cycle to start FST tracing")
 386     parser.add_argument("--trace-end",    default=-1,
 387                         help="Cycle to end FST tracing")
 388     args = parser.parse_args()
 389
 390     sim_config = SimConfig(default_clk="sys_clk")
 391     sim_config.add_module("serial2console", "serial")
 392
 393     for i in range(2):
 394         soc = LibreSoCSim(cpu=args.cpu, debug=args.debug)
 395         builder = Builder(soc,compile_gateware = i!=0)
 396         builder.build(sim_config=sim_config,
 397             run         = i!=0,
 398             trace       = args.trace,
 399             trace_start = int(args.trace_start),
 400             trace_end   = int(args.trace_end),
 401             trace_fst   = 0)
 402         os.chdir("../")
 403
 404 if __name__ == "__main__":
 405     main()