src/soc/litex/florent/sim.py

   1 #!/usr/bin/env python3
   2
   3 import os
   4 import argparse
   5
   6 from migen import Signal, FSM
   7
   8 from litex.build.generic_platform import Pins, Subsignal
   9 from litex.build.sim import SimPlatform
  10 from litex.build.io import CRG
  11 from litex.build.sim.config import SimConfig
  12
  13 from litex.soc.integration.soc import SoCRegion
  14 from litex.soc.integration.soc_core import SoCCore
  15 from litex.soc.integration.builder import Builder
  16
  17 from litex.tools.litex_sim import Platform
  18
  19 from libresoc import LibreSoC
  20 from microwatt import Microwatt
  21
  22 # LibreSoCSim -----------------------------------------------------------------
  23
  24 class LibreSoCSim(SoCCore):
  25     def __init__(self, cpu="libresoc", debug=False):
  26         assert cpu in ["libresoc", "microwatt"]
  27         platform     = Platform()
  28         sys_clk_freq = int(1e6)
  29
  30         # SoCCore -------------------------------------------------------------
  31         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
  32             cpu_type                 = "microwatt",
  33             cpu_cls                  = LibreSoC   if cpu == "libresoc" \
  34                                        else Microwatt,
  35             uart_name                = "sim",
  36             integrated_rom_size      = 0x10000,
  37             integrated_main_ram_size = 0x10000000) # 256MB
  38         self.platform.name = "sim"
  39
  40         # CRG -----------------------------------------------------------------
  41         self.submodules.crg = CRG(platform.request("sys_clk"))
  42
  43         # Debug ---------------------------------------------------------------
  44         if debug:
  45             uptime = Signal(64)
  46             self.sync += uptime.eq(uptime + 1)
  47             self.sync += If(self.cpu.ibus.stb & self.cpu.ibus.ack &
  48                             self.cpu.ibus.we,
  49                 Display("[%06x] iadr: %8x, s %01x w %016x",
  50                     uptime,
  51                     self.cpu.ibus.adr,
  52                     self.cpu.ibus.sel,
  53                     self.cpu.ibus.dat_w,
  54                 )
  55             )
  56             self.sync += If(self.cpu.ibus.stb & self.cpu.ibus.ack &
  57                             ~self.cpu.ibus.we,
  58                 Display("[%06x] iadr: %8x, s %01x r %016x",
  59                     uptime,
  60                     self.cpu.ibus.adr,
  61                     self.cpu.ibus.sel,
  62                     self.cpu.ibus.dat_r
  63                 )
  64             )
  65             self.sync += If(self.cpu.dbus.stb & self.cpu.dbus.ack,
  66                 Display("[%06x] dadr: %8x, we %d s %01x w %016x r: %016x",
  67                     uptime,
  68                     self.cpu.dbus.adr,
  69                     self.cpu.dbus.we,
  70                     self.cpu.dbus.sel,
  71                     self.cpu.dbus.dat_w,
  72                     self.cpu.dbus.dat_r
  73                 )
  74             )
  75             # Stop after 20000 cycles
  76             self.sync += If(uptime == 100000, Finish())
  77
  78 # Build -----------------------------------------------------------------------
  79
  80 def main():
  81     parser = argparse.ArgumentParser(description="LiteX LibreSoC CPU Sim")
  82     parser.add_argument("--cpu",          default="libresoc",
  83                         help="CPU to use: libresoc (default) or microwatt")
  84     parser.add_argument("--debug",        action="store_true",
  85                         help="Enable debug traces")
  86     parser.add_argument("--trace",        action="store_true",
  87                         help="Enable tracing")
  88     parser.add_argument("--trace-start",  default=0,
  89                         help="Cycle to start FST tracing")
  90     parser.add_argument("--trace-end",    default=-1,
  91                         help="Cycle to end FST tracing")
  92     args = parser.parse_args()
  93
  94     sim_config = SimConfig(default_clk="sys_clk")
  95     sim_config.add_module("serial2console", "serial")
  96
  97     for i in range(2):
  98         soc = LibreSoCSim(cpu=args.cpu, debug=args.debug)
  99         builder = Builder(soc,compile_gateware = i!=0)
 100         builder.build(sim_config=sim_config,
 101             run         = i!=0,
 102             trace       = args.trace,
 103             trace_start = int(args.trace_start),
 104             trace_end   = int(args.trace_end),
 105             trace_fst   = 0)
 106         os.chdir("../")
 107
 108 if __name__ == "__main__":
 109     main()