src/soc/minerva/isa.py

   1 from soc.minerva.csr import CSRAccess
   2
   3
   4 __all__ = [
   5     "Opcode", "Funct3", "Funct7", "Funct12", "CSRIndex", "Cause",
   6     "flat_layout", "misa_layout", "mstatus_layout", "mtvec_layout", "mepc_layout",
   7     "mip_layout", "mie_layout", "mcause_layout", "dcsr_layout", "tdata1_layout"
   8 ]
   9
  10 class Opcode:
  11     LUI       = 0b01101
  12     AUIPC     = 0b00101
  13     JAL       = 0b11011
  14     JALR      = 0b11001
  15     BRANCH    = 0b11000
  16     LOAD      = 0b00000
  17     STORE     = 0b01000
  18     OP_IMM_32 = 0b00100
  19     OP_32     = 0b01100
  20     MISC_MEM  = 0b00011
  21     SYSTEM    = 0b11100
  22
  23
  24 class Funct3:
  25     BEQ  = B  = ADD  = FENCE  = PRIV   = MUL    = 0b000
  26     BNE  = H  = SLL  = FENCEI = CSRRW  = MULH   = 0b001
  27     _    = W  = SLT  = _      = CSRRS  = MULHSU = 0b010
  28     _    = _  = SLTU = _      = CSRRC  = MULHU  = 0b011
  29     BLT  = BU = XOR  = _      = _      = DIV    = 0b100
  30     BGE  = HU = SR   = _      = CSRRWI = DIVU   = 0b101
  31     BLTU = _  = OR   = _      = CSRRSI = REM    = 0b110
  32     BGEU = _  = AND  = _      = CSRRCI = REMU   = 0b111
  33
  34
  35 class Funct7:
  36     SRL = ADD = 0b0000000
  37     MULDIV    = 0b0000001
  38     SRA = SUB = 0b0100000
  39
  40
  41 class Funct12:
  42     ECALL  = 0b000000000000
  43     EBREAK = 0b000000000001
  44     MRET   = 0b001100000010
  45     WFI    = 0b000100000101
  46
  47
  48 class CSRIndex:
  49     MVENDORID   = 0xF11
  50     MARCHID     = 0xF12
  51     MIMPID      = 0xF13
  52     MHARTID     = 0xF14
  53     MSTATUS     = 0x300
  54     MISA        = 0x301
  55     MEDELEG     = 0x302
  56     MIDELEG     = 0x303
  57     MIE         = 0x304
  58     MTVEC       = 0x305
  59     MCOUTEREN   = 0x306
  60     MSCRATCH    = 0x340
  61     MEPC        = 0x341
  62     MCAUSE      = 0x342
  63     MTVAL       = 0x343
  64     MIP         = 0x344
  65     # µarch specific
  66     IRQ_MASK    = 0x330
  67     IRQ_PENDING = 0x360
  68     # trigger module
  69     TSELECT     = 0x7a0
  70     TDATA1      = 0x7a1
  71     TDATA2      = 0x7a2
  72     TDATA3      = 0x7a3
  73     TINFO       = 0x7a4
  74     MCONTEXT    = 0x7a8
  75     # debug module
  76     DCSR        = 0x7b0
  77     DPC         = 0x7b1
  78
  79
  80 class Cause:
  81     FETCH_MISALIGNED     = 0
  82     FETCH_ACCESS_FAULT   = 1
  83     ILLEGAL_INSTRUCTION  = 2
  84     BREAKPOINT           = 3
  85     LOAD_MISALIGNED      = 4
  86     LOAD_ACCESS_FAULT    = 5
  87     STORE_MISALIGNED     = 6
  88     STORE_ACCESS_FAULT   = 7
  89     ECALL_FROM_U         = 8
  90     ECALL_FROM_S         = 9
  91     ECALL_FROM_M         = 11
  92     FETCH_PAGE_FAULT     = 12
  93     LOAD_PAGE_FAULT      = 13
  94     STORE_PAGE_FAULT     = 15
  95     # interrupts
  96     U_SOFTWARE_INTERRUPT = 0
  97     S_SOFTWARE_INTERRUPT = 1
  98     M_SOFTWARE_INTERRUPT = 3
  99     U_TIMER_INTERRUPT    = 4
 100     S_TIMER_INTERRUPT    = 5
 101     M_TIMER_INTERRUPT    = 7
 102     U_EXTERNAL_INTERRUPT = 8
 103     S_EXTERNAL_INTERRUPT = 9
 104     M_EXTERNAL_INTERRUPT = 11
 105
 106
 107 # CSR layouts
 108
 109 flat_layout = [
 110     ("value", 32, CSRAccess.WARL)
 111 ]
 112
 113
 114 misa_layout = [
 115     ("extensions", 26, CSRAccess.WARL),
 116     ("wiri0",       4, CSRAccess.WIRI),
 117     ("mxl",         2, CSRAccess.WARL)
 118 ]
 119
 120
 121 mstatus_layout = [
 122     ("uie",   1, CSRAccess.WARL), # User Interrupt Enable
 123     ("sie",   1, CSRAccess.WARL), # Supervisor Interrupt Enable
 124     ("wpri0", 1, CSRAccess.WPRI),
 125     ("mie",   1, CSRAccess.WARL), # Machine Interrupt Enable
 126     ("upie",  1, CSRAccess.WARL), # User Previous Interrupt Enable
 127     ("spie",  1, CSRAccess.WARL), # Supervisor Previous Interrupt Enable
 128     ("wpri1", 1, CSRAccess.WPRI),
 129     ("mpie",  1, CSRAccess.WARL), # Machine Previous Interrupt Enable
 130     ("spp",   1, CSRAccess.WARL), # Supervisor Previous Privilege
 131     ("wpri2", 2, CSRAccess.WPRI),
 132     ("mpp",   2, CSRAccess.WARL), # Machine Previous Privilege
 133     ("fs",    2, CSRAccess.WARL), # FPU Status
 134     ("xs",    2, CSRAccess.WARL), # user-mode eXtensions Status
 135     ("mprv",  1, CSRAccess.WARL), # Modify PRiVilege
 136     ("sum",   1, CSRAccess.WARL), # Supervisor User Memory access
 137     ("mxr",   1, CSRAccess.WARL), # Make eXecutable Readable
 138     ("tvm",   1, CSRAccess.WARL), # Trap Virtual Memory
 139     ("tw",    1, CSRAccess.WARL), # Timeout Wait
 140     ("tsr",   1, CSRAccess.WARL), # Trap SRET
 141     ("wpri3", 8, CSRAccess.WPRI),
 142     ("sd",    1, CSRAccess.WARL)  # State Dirty (set if XS or FS are set to dirty)
 143 ]
 144
 145
 146 mtvec_layout = [
 147     ("mode",  2, CSRAccess.WARL),
 148     ("base", 30, CSRAccess.WARL)
 149 ]
 150
 151
 152 mepc_layout = [
 153     ("zero",  2, CSRAccess.WIRI),  # 16-bit instructions are not supported
 154     ("base", 30, CSRAccess.WARL)
 155 ]
 156
 157
 158 mip_layout = [
 159     ("usip",   1, CSRAccess.WARL),
 160     ("ssip",   1, CSRAccess.WARL),
 161     ("wiri0",  1, CSRAccess.WIRI),
 162     ("msip",   1, CSRAccess.WARL),
 163     ("utip",   1, CSRAccess.WARL),
 164     ("stip",   1, CSRAccess.WARL),
 165     ("wiri1",  1, CSRAccess.WIRI),
 166     ("mtip",   1, CSRAccess.WARL),
 167     ("ueip",   1, CSRAccess.WARL),
 168     ("seip",   1, CSRAccess.WARL),
 169     ("wiri2",  1, CSRAccess.WIRI),
 170     ("meip",   1, CSRAccess.WARL),
 171     ("wiri3", 20, CSRAccess.WIRI)
 172 ]
 173
 174
 175 mie_layout = [
 176     ("usie",   1, CSRAccess.WARL),
 177     ("ssie",   1, CSRAccess.WARL),
 178     ("wpri0",  1, CSRAccess.WPRI),
 179     ("msie",   1, CSRAccess.WARL),
 180     ("utie",   1, CSRAccess.WARL),
 181     ("stie",   1, CSRAccess.WARL),
 182     ("wpri1",  1, CSRAccess.WPRI),
 183     ("mtie",   1, CSRAccess.WARL),
 184     ("ueie",   1, CSRAccess.WARL),
 185     ("seie",   1, CSRAccess.WARL),
 186     ("wpri2",  1, CSRAccess.WPRI),
 187     ("meie",   1, CSRAccess.WARL),
 188     ("wpri3", 20, CSRAccess.WPRI)
 189 ]
 190
 191
 192 mcause_layout = [
 193     ("ecode",    31, CSRAccess.WARL),
 194     ("interrupt", 1, CSRAccess.WARL)
 195 ]
 196
 197
 198 dcsr_layout = [
 199     ("prv",        2, CSRAccess.WARL), # Privilege level before Debug Mode was entered
 200     ("step",       1, CSRAccess.WARL), # Execute a single instruction and re-enter Debug Mode
 201     ("nmip",       1, CSRAccess.WLRL), # A non-maskable interrupt is pending
 202     ("mprven",     1, CSRAccess.WARL), # Use mstatus.mprv in Debug Mode
 203     ("zero0",      1, CSRAccess.WPRI),
 204     ("cause",      3, CSRAccess.WLRL), # Explains why Debug Mode was entered
 205     ("stoptime",   1, CSRAccess.WARL), # Stop timer increment during Debug Mode
 206     ("stopcount",  1, CSRAccess.WARL), # Stop counter increment during Debug Mode
 207     ("stepie",     1, CSRAccess.WARL), # Enable interrupts during single stepping
 208     ("ebreaku",    1, CSRAccess.WARL), # EBREAKs in U-mode enter Debug Mode
 209     ("ebreaks",    1, CSRAccess.WARL), # EBREAKs in S-mode enter Debug Mode
 210     ("zero1",      1, CSRAccess.WPRI),
 211     ("ebreakm",    1, CSRAccess.WARL), # EBREAKs in M-mode enter Debug Mode
 212     ("zero2",     12, CSRAccess.WPRI),
 213     ("xdebugver",  4, CSRAccess.WLRL)  # External Debug specification version
 214 ]
 215
 216
 217 tdata1_layout = [
 218     ("data",  27, CSRAccess.WARL),
 219     ("dmode",  1, CSRAccess.WARL),
 220     ("type",   4, CSRAccess.WARL)
 221 ]