src/soc/minerva/units/debug/top.py

   1 from nmigen import Elaboratable, Module, Signal, Record
   2
   3
   4 from ...csr import AutoCSR, CSR
   5 from ...wishbone import wishbone_layout
   6 from .controller import DebugController
   7 from .jtag import JTAGReg, dtmcs_layout, dmi_layout, jtag_layout
   8 from .regfile import DebugRegisterFile
   9 from .wbmaster import wishbone_layout, DebugWishboneMaster
  10
  11 # FIXME: figure out where JTAGTap is
  12 # from jtagtap import JTAGTap
  13
  14
  15 class JTAGTap:
  16     def __init__(self):
  17         raise NotImplementedError(
  18             "jtagtap package not found: figure out where JTAGTap is")
  19
  20
  21 __all__ = ["DebugUnit"]
  22
  23
  24 jtag_regs = {
  25     JTAGReg.IDCODE: [("value", 32)],
  26     JTAGReg.DTMCS:  dtmcs_layout,
  27     JTAGReg.DMI:    dmi_layout
  28 }
  29
  30
  31 class DebugUnit(Elaboratable, AutoCSR):
  32     def __init__(self):
  33         self.jtag = Record(jtag_layout)
  34         self.dbus = Record(wishbone_layout)
  35
  36         self.trigger_haltreq = Signal()
  37
  38         self.x_ebreak = Signal()
  39         self.x_pc = Signal(32)
  40         self.x_stall = Signal()
  41
  42         self.m_branch_taken = Signal()
  43         self.m_branch_target = Signal(32)
  44         self.m_mret = Signal()
  45         self.m_exception = Signal()
  46         self.m_pc = Signal(32)
  47         self.m_valid = Signal()
  48         self.mepc_r_base = Signal(30)
  49         self.mtvec_r_base = Signal(30)
  50
  51         self.dcsr_step = Signal()
  52         self.dcsr_ebreakm = Signal()
  53         self.dpc_value = Signal(32)
  54
  55         self.halt = Signal()
  56         self.halted = Signal()
  57         self.killall = Signal()
  58         self.resumereq = Signal()
  59         self.resumeack = Signal()
  60
  61         self.dbus_busy = Signal()
  62
  63         self.csrf_addr = Signal(12)
  64         self.csrf_re = Signal()
  65         self.csrf_dat_r = Signal(32)
  66         self.csrf_we = Signal()
  67         self.csrf_dat_w = Signal(32)
  68
  69         self.gprf_addr = Signal(5)
  70         self.gprf_re = Signal()
  71         self.gprf_dat_r = Signal(32)
  72         self.gprf_we = Signal()
  73         self.gprf_dat_w = Signal(32)
  74
  75     def elaborate(self, platform):
  76         m = Module()
  77
  78         tap = m.submodules.tap = JTAGTap(jtag_regs)
  79         regfile = m.submodules.regfile = DebugRegisterFile(
  80             tap.regs[JTAGReg.DMI])
  81         controller = m.submodules.controller = DebugController(regfile)
  82         wbmaster = m.submodules.wbmaster = DebugWishboneMaster(regfile)
  83
  84         m.d.comb += [
  85             tap.port.connect(self.jtag),
  86             # Usurpate a Spike core for now.
  87             tap.regs[JTAGReg.IDCODE].r.eq(0x10e31913),
  88             tap.regs[JTAGReg.DTMCS].r.eq(0x61)  # (abits=6, version=1) TODO
  89         ]
  90
  91         m.d.comb += [
  92             controller.trigger_haltreq.eq(self.trigger_haltreq),
  93
  94             controller.x_ebreak.eq(self.x_ebreak),
  95             controller.x_pc.eq(self.x_pc),
  96             controller.x_stall.eq(self.x_stall),
  97
  98             controller.m_branch_taken.eq(self.m_branch_taken),
  99             controller.m_branch_target.eq(self.m_branch_target),
 100             controller.m_pc.eq(self.m_pc),
 101             controller.m_valid.eq(self.m_valid),
 102
 103             self.halt.eq(controller.halt),
 104             controller.halted.eq(self.halted),
 105             self.killall.eq(controller.killall),
 106             self.resumereq.eq(controller.resumereq),
 107             controller.resumeack.eq(self.resumeack),
 108
 109             self.dcsr_step.eq(controller.dcsr.r.step),
 110             self.dcsr_ebreakm.eq(controller.dcsr.r.ebreakm),
 111             self.dpc_value.eq(controller.dpc.r.value),
 112
 113             self.csrf_addr.eq(controller.csrf_addr),
 114             self.csrf_re.eq(controller.csrf_re),
 115             controller.csrf_dat_r.eq(self.csrf_dat_r),
 116             self.csrf_we.eq(controller.csrf_we),
 117             self.csrf_dat_w.eq(controller.csrf_dat_w),
 118
 119             self.gprf_addr.eq(controller.gprf_addr),
 120             self.gprf_re.eq(controller.gprf_re),
 121             controller.gprf_dat_r.eq(self.gprf_dat_r),
 122             self.gprf_we.eq(controller.gprf_we),
 123             self.gprf_dat_w.eq(controller.gprf_dat_w),
 124         ]
 125
 126         m.d.comb += [
 127             wbmaster.bus.connect(self.dbus),
 128             self.dbus_busy.eq(wbmaster.dbus_busy)
 129         ]
 130
 131         return m