add misaligned load through MMU (which is incorrectly succeeding without error)
[soc.git] / src / soc / minerva / units / predict.py
1 from nmigen import Elaboratable, Module, Signal
2
3
4 __all__ = ["BranchPredictor"]
5
6
7 class BranchPredictor(Elaboratable):
8 def __init__(self):
9 self.d_branch = Signal()
10 self.d_jump = Signal()
11 self.d_offset = Signal((32, True))
12 self.d_pc = Signal(32)
13 self.d_rs1_re = Signal()
14
15 self.d_branch_taken = Signal()
16 self.d_branch_target = Signal(32)
17 self.d_fetch_misaligned = Signal()
18
19 def elaborate(self, platform):
20 m = Module()
21
22 with m.If(self.d_branch):
23 # Backward conditional branches are predicted as taken.
24 # Forward conditional branches are predicted as not taken.
25 m.d.comb += self.d_branch_taken.eq(self.d_offset[-1])
26 with m.Else():
27 # Direct jumps are predicted as taken.
28 # Other branch types (ie. indirect jumps, exceptions) are not predicted.
29 m.d.comb += self.d_branch_taken.eq(self.d_jump & ~self.d_rs1_re)
30
31 m.d.comb += [
32 self.d_branch_target.eq(self.d_pc + self.d_offset),
33 self.d_fetch_misaligned.eq(self.d_branch_target[:2].bool())
34 ]
35
36 return m