src/soc/minerva/wishbone.py

   1 from nmigen import Array, Elaboratable, Module, Record, Signal
   2 from nmigen.hdl.rec import DIR_FANIN, DIR_FANOUT, DIR_NONE
   3 from nmigen.lib.coding import PriorityEncoder
   4 from nmigen.utils import log2_int
   5
   6
   7 __all__ = ["Cycle", "make_wb_layout", "WishboneArbiter"]
   8
   9
  10 class Cycle:
  11     CLASSIC   = 0
  12     CONSTANT  = 1
  13     INCREMENT = 2
  14     END       = 7
  15
  16
  17 def make_wb_layout(spec):
  18     addr_wid, mask_wid, data_wid = spec.addr_wid, spec.mask_wid, spec.reg_wid
  19     adr_lsbs = log2_int(mask_wid) # LSBs of addr covered by mask
  20     badwid = spec.addr_wid-adr_lsbs    # MSBs (not covered by mask)
  21
  22     return [
  23     ("adr",   badwid  , DIR_FANOUT),
  24     ("dat_w", data_wid, DIR_FANOUT),
  25     ("dat_r", data_wid, DIR_FANIN),
  26     ("sel",   mask_wid, DIR_FANOUT),
  27     ("cyc",           1, DIR_FANOUT),
  28     ("stb",           1, DIR_FANOUT),
  29     ("ack",           1, DIR_FANIN),
  30     ("we",            1, DIR_FANOUT),
  31     ("cti",           3, DIR_FANOUT),
  32     ("bte",           2, DIR_FANOUT),
  33     ("err",           1, DIR_FANIN)
  34     ]
  35
  36
  37 class WishboneArbiter(Elaboratable):
  38     def __init__(self, pspec):
  39         self.bus = Record(make_wb_layout(pspec))
  40         self._port_map = dict()
  41
  42     def port(self, priority):
  43         if not isinstance(priority, int) or priority < 0:
  44             raise TypeError("Priority must be a non-negative "\
  45                             "integer, not '{!r}'" .format(priority))
  46         if priority in self._port_map:
  47             raise ValueError("Conflicting priority: '{!r}'".format(priority))
  48         port = self._port_map[priority] = Record.like(self.bus)
  49         return port
  50
  51     def elaborate(self, platform):
  52         m = Module()
  53
  54         ports = [port for priority, port in sorted(self._port_map.items())]
  55
  56         for port in ports:
  57             m.d.comb += port.dat_r.eq(self.bus.dat_r)
  58
  59         bus_pe = m.submodules.bus_pe = PriorityEncoder(len(ports))
  60         with m.If(~self.bus.cyc):
  61             for j, port in enumerate(ports):
  62                 m.d.sync += bus_pe.i[j].eq(port.cyc)
  63
  64         source = Array(ports)[bus_pe.o]
  65         m.d.comb += [
  66             self.bus.adr.eq(source.adr),
  67             self.bus.dat_w.eq(source.dat_w),
  68             self.bus.sel.eq(source.sel),
  69             self.bus.cyc.eq(source.cyc),
  70             self.bus.stb.eq(source.stb),
  71             self.bus.we.eq(source.we),
  72             self.bus.cti.eq(source.cti),
  73             self.bus.bte.eq(source.bte),
  74             source.ack.eq(self.bus.ack),
  75             source.err.eq(self.bus.err)
  76         ]
  77
  78         return m