src/soc/minerva/wishbone.py

   1 from nmigen import Array, Elaboratable, Module, Record, Signal
   2 from nmigen.hdl.rec import DIR_FANIN, DIR_FANOUT, DIR_NONE
   3 from nmigen.lib.coding import PriorityEncoder
   4 from nmigen.utils import log2_int
   5
   6
   7 __all__ = ["Cycle", "wishbone_layout", "make_wb_layout", "WishboneArbiter"]
   8
   9
  10 class Cycle:
  11     CLASSIC   = 0
  12     CONSTANT  = 1
  13     INCREMENT = 2
  14     END       = 7
  15
  16
  17 def make_wb_layout(addr_wid, mask_wid, data_wid):
  18     adr_lsbs = log2_int(mask_wid) # LSBs of addr covered by mask
  19     badwid = addr_wid-adr_lsbs    # MSBs (not covered by mask)
  20
  21     return [
  22     ("adr",   badwid  , DIR_FANOUT),
  23     ("dat_w", data_wid, DIR_FANOUT),
  24     ("dat_r", data_wid, DIR_FANIN),
  25     ("sel",   mask_wid, DIR_FANOUT),
  26     ("cyc",           1, DIR_FANOUT),
  27     ("stb",           1, DIR_FANOUT),
  28     ("ack",           1, DIR_FANIN),
  29     ("we",            1, DIR_FANOUT),
  30     ("cti",           3, DIR_FANOUT),
  31     ("bte",           2, DIR_FANOUT),
  32     ("err",           1, DIR_FANIN)
  33     ]
  34
  35 wishbone_layout = make_wb_layout(32, 4, 32)
  36
  37
  38 class WishboneArbiter(Elaboratable):
  39     def __init__(self):
  40         self.bus = Record(wishbone_layout)
  41         self._port_map = dict()
  42
  43     def port(self, priority):
  44         if not isinstance(priority, int) or priority < 0:
  45             raise TypeError("Priority must be a non-negative "\
  46                             "integer, not '{!r}'" .format(priority))
  47         if priority in self._port_map:
  48             raise ValueError("Conflicting priority: '{!r}'".format(priority))
  49         port = self._port_map[priority] = Record.like(self.bus)
  50         return port
  51
  52     def elaborate(self, platform):
  53         m = Module()
  54
  55         ports = [port for priority, port in sorted(self._port_map.items())]
  56
  57         for port in ports:
  58             m.d.comb += port.dat_r.eq(self.bus.dat_r)
  59
  60         bus_pe = m.submodules.bus_pe = PriorityEncoder(len(ports))
  61         with m.If(~self.bus.cyc):
  62             for j, port in enumerate(ports):
  63                 m.d.sync += bus_pe.i[j].eq(port.cyc)
  64
  65         source = Array(ports)[bus_pe.o]
  66         m.d.comb += [
  67             self.bus.adr.eq(source.adr),
  68             self.bus.dat_w.eq(source.dat_w),
  69             self.bus.sel.eq(source.sel),
  70             self.bus.cyc.eq(source.cyc),
  71             self.bus.stb.eq(source.stb),
  72             self.bus.we.eq(source.we),
  73             self.bus.cti.eq(source.cti),
  74             self.bus.bte.eq(source.bte),
  75             source.ack.eq(self.bus.ack),
  76             source.err.eq(self.bus.err)
  77         ]
  78
  79         return m