src/soc/regfile/regfiles.py

   1 # POWER9 Register Files
   2 """POWER9 regfiles
   3
   4 Defines the following register files:
   5
   6     * INT regfile   - 32x 64-bit
   7     * SPR regfile   - 110x 64-bit
   8     * CR regfile    - CR0-7
   9     * XER regfile   - XER.so, XER.ca/ca32, XER.ov/ov32
  10     * FAST regfile  - CTR, LR, TAR, SRR1, SRR2
  11     * STATE regfile  - PC, MSR, (SimpleV VL later)
  12
  13 Note: this should NOT have name conventions hard-coded (dedicated ports per
  14 regname).  However it is convenient for now.
  15
  16 Links:
  17
  18 * https://bugs.libre-soc.org/show_bug.cgi?id=345
  19 * https://bugs.libre-soc.org/show_bug.cgi?id=351
  20 * https://libre-soc.org/3d_gpu/architecture/regfile/
  21 * https://libre-soc.org/openpower/isatables/sprs.csv
  22 """
  23
  24 # TODO
  25
  26 from soc.regfile.regfile import RegFile, RegFileArray, RegFileMem
  27 from soc.regfile.virtual_port import VirtualRegPort
  28 from soc.decoder.power_enums import SPR
  29
  30
  31 # "State" Regfile
  32 class StateRegs(RegFileArray):
  33     """StateRegs
  34
  35     State regfile  - PC, MSR, DEC, TB and later SimpleV VL
  36
  37     * QTY 4of 64-bit registers
  38     * 5R4W
  39     * Array-based unary-indexed (not binary-indexed)
  40     * write-through capability (read on same cycle as write)
  41
  42     Note: d_wr1 d_rd1 are for use by the decoder, to get at the PC.
  43     will probably have to also add one so it can get at the MSR as well.
  44     (d_rd2)
  45
  46     Note: r/w state are used by SPR for MTSPR / MFSPR.
  47     Note: r/w issue are used by issuer to increment/decrement TB/DEC.
  48     """
  49     PC = 0
  50     MSR = 1
  51     DEC = 2
  52     TB = 3
  53     def __init__(self):
  54         super().__init__(64, 4)
  55         self.w_ports = {'nia': self.write_port("nia"),
  56                         'msr': self.write_port("msr"),
  57                         'state': self.read_port("state"), # writing DEC/TB
  58                         'issue': self.read_port("issue"), # writing DEC/TB
  59                         'd_wr1': self.write_port("d_wr1")} # writing PC (issuer)
  60         self.r_ports = {'cia': self.read_port("cia"), # reading PC (issuer)
  61                         'msr': self.read_port("msr"), # reading MSR (issuer)
  62                         'state': self.read_port("state"), # reading DEC/TB
  63                         'issue': self.read_port("issue"), # reading DEC/TB
  64                         }
  65
  66
  67 # Integer Regfile
  68 class IntRegs(RegFileMem): #class IntRegs(RegFileArray):
  69     """IntRegs
  70
  71     * QTY 32of 64-bit registers
  72     * 3R2W
  73     * Array-based unary-indexed (not binary-indexed)
  74     * write-through capability (read on same cycle as write)
  75     """
  76     def __init__(self):
  77         super().__init__(64, 32)
  78         self.w_ports = {'o': self.write_port("dest1"),
  79                         #'o1': self.write_port("dest2") # for now (LD/ST update)
  80                         }
  81         self.r_ports = {'ra': self.read_port("src1"),
  82                         'rb': self.read_port("src2"),
  83                         'rc': self.read_port("src3"),
  84                         'dmi': self.read_port("dmi")} # needed for Debug (DMI)
  85
  86
  87 # Fast SPRs Regfile
  88 class FastRegs(RegFileMem): #RegFileArray):
  89     """FastRegs
  90
  91     FAST regfile  - CTR, LR, TAR, SRR1, SRR2, XER
  92
  93     * QTY 6of 64-bit registers
  94     * 2R1W
  95     * Array-based unary-indexed (not binary-indexed)
  96     * write-through capability (read on same cycle as write)
  97     """
  98     CTR = 0
  99     LR = 1
 100     TAR = 2
 101     SRR0 = 3
 102     SRR1 = 4
 103     XER = 5 # non-XER bits
 104     def __init__(self):
 105         super().__init__(64, 6)
 106         self.w_ports = {'fast1': self.write_port("dest1"),
 107                        }
 108         self.r_ports = {'fast1': self.read_port("src1"),
 109                         'fast2': self.read_port("src2"),
 110                         }
 111
 112
 113 # CR Regfile
 114 class CRRegs(VirtualRegPort):
 115     """Condition Code Registers (CR0-7)
 116
 117     * QTY 8of 8-bit registers
 118     * 3R1W 4-bit-wide with additional 1R1W for the "full" 32-bit width
 119     * Array-based unary-indexed (not binary-indexed)
 120     * write-through capability (read on same cycle as write)
 121     """
 122     def __init__(self):
 123         super().__init__(32, 8, rd2=True)
 124         self.w_ports = {'full_cr': self.full_wr, # 32-bit (masked, 8-en lines)
 125                         'cr_a': self.write_port("dest1"), # 4-bit, unary-indexed
 126                         'cr_b': self.write_port("dest2")} # 4-bit, unary-indexed
 127         self.r_ports = {'full_cr': self.full_rd, # 32-bit (masked, 8-en lines)
 128                         'full_cr_dbg': self.full_rd2, # for DMI
 129                         'cr_a': self.read_port("src1"),
 130                         'cr_b': self.read_port("src2"),
 131                         'cr_c': self.read_port("src3")}
 132
 133
 134 # XER Regfile
 135 class XERRegs(VirtualRegPort):
 136     """XER Registers (SO, CA/CA32, OV/OV32)
 137
 138     * QTY 3of 2-bit registers
 139     * 3R3W 2-bit-wide with additional 1R1W for the "full" 6-bit width
 140     * Array-based unary-indexed (not binary-indexed)
 141     * write-through capability (read on same cycle as write)
 142     """
 143     SO=0 # this is actually 2-bit but we ignore 1 bit of it
 144     CA=1 # CA and CA32
 145     OV=2 # OV and OV32
 146     def __init__(self):
 147         super().__init__(6, 3)
 148         self.w_ports = {'full_xer': self.full_wr, # 6-bit (masked, 3-en lines)
 149                         'xer_so': self.write_port("dest1"),
 150                         'xer_ca': self.write_port("dest2"),
 151                         'xer_ov': self.write_port("dest3")}
 152         self.r_ports = {'full_xer': self.full_rd, # 6-bit (masked, 3-en lines)
 153                         'xer_so': self.read_port("src1"),
 154                         'xer_ca': self.read_port("src2"),
 155                         'xer_ov': self.read_port("src3")}
 156
 157
 158 # SPR Regfile
 159 class SPRRegs(RegFileMem):
 160     """SPRRegs
 161
 162     * QTY len(SPRs) 64-bit registers
 163     * 1R1W
 164     * binary-indexed but REQUIRES MAPPING
 165     * write-through capability (read on same cycle as write)
 166     """
 167     def __init__(self):
 168         n_sprs = len(SPR)
 169         super().__init__(width=64, depth=n_sprs)
 170         self.w_ports = {'spr1': self.write_port("spr1")}
 171         self.r_ports = {'spr1': self.read_port("spr1")}
 172
 173
 174 # class containing all regfiles: int, cr, xer, fast, spr
 175 class RegFiles:
 176     def __init__(self):
 177         self.rf = {}
 178         for (name, kls) in [('int', IntRegs),
 179                             ('cr', CRRegs),
 180                             ('xer', XERRegs),
 181                             ('fast', FastRegs),
 182                             ('state', StateRegs),
 183                             ('spr', SPRRegs),]:
 184             rf = self.rf[name] = kls()
 185             setattr(self, name, rf)
 186
 187     def elaborate_into(self, m, platform):
 188         for (name, rf) in self.rf.items():
 189             setattr(m.submodules, name, rf)
 190         return m
 191